PPC460EX-SUB800N AMCC, PPC460EX-SUB800N Datasheet - Page 70
PPC460EX-SUB800N
Manufacturer Part Number
PPC460EX-SUB800N
Description
Manufacturer
AMCC
Datasheet
1.PPC460EX-SUB800N.pdf
(106 pages)
- Current page: 70 of 106
- Download datasheet (2Mb)
460EX – PPC460EX Embedded Processor
Table 9. Signal Functional Description (Part 7 of 10)
Notes:
1. Receiver input has hysteresis
2. Must pull up (recommended value is 3kΩ to OV
3. Must pull down (recommended value is 1kΩ to GND)
4. If not used, must pull up (recommended value is 3kΩ for LVTTL or 8.2kΩ for PCI to OV
5. If not used, must pull down (recommended value is 1kΩ)
6. Strapping input during reset; pull-up (recommended value is 3kΩ to OV
70
UART Peripheral Interface
The UART interface can be configured as follows:
1. One 8-pin, where n = 0
2. Two 4-pin, where n = 0 & 1
3. Four 2-pin, where n = 0 & 1 & 2 & 3
UARTSerClk
UARTnRx
UARTnTx
UARTnDCD
UARTnDSR
UARTnCTS
UARTnDTR
UARTnRTS
UARTnRI
IIC Peripheral Interface (n = 0 and 1)
IICnSClk
IICnSData
USB 2.0 OTG (Device or Host) Interface
USB2DD7:0
USB2DDir
USB2DNext
USB2DStop
USB2DClk
GND) required
Signal Name
This input provides an alternative to the internally generated
serial clock. It is used in cases where the allowable internally
generated clock rates are not satisfactory.
Receive data.
Transmit data.
Data Carrier Detect.
Data Set Ready.
Clear To Send.
Data Terminal Ready.
Request To Send.
Ring Indicator.
IIC0 Serial Clock.
IIC0 Serial Data.
Bidirectional Device data bus.
Transfer direction. PHY has data to transfer.
Next transfer. Input signal from the PHY:
Stop transfer. Output signal to the PHY:
USB 2.0 OTG clock—60MHz.
Receiving—ready to accept the next data transfer.
Transmitting—a new byte is ready to send.
Receiving—stop transferring data.
Transmitting—the last byte of data has been sent.
DD
or 8.2kΩ for PCI to OV
Description
DD
DD
) or pull-down (recommended value is 1kΩ to
or equivalent.
Preliminary Data Sheet
DD
Revision 1.19 – June 17, 2009
or equivalent.
I/O
I/O
I/O
I/O
O
O
O
O
I
I
I
I
I
I
I
I
I
3.3V tolerant
3.3V tolerant
3.3V tolerant
3.3V tolerant
3.3V tolerant
3.3V LVTTL
3.3V LVTTL
3.3V LVTTL
3.3V LVTTL
3.3V LVTTL
3.3V LVTTL
3.3V LVTTL
3.3V LVTTL
3.3V LVTTL
3.3V LVTTL
3.3V LVTTL
2.5V CMOS
2.5V CMOS
2.5V CMOS
2.5V CMOS
2.5V CMOS
w/pull-up
Type
AMCC Proprietary
Notes
1, 2
1, 5
1
6
6
6
2
1
1
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