PPC460EX-SUB800N AMCC, PPC460EX-SUB800N Datasheet - Page 82

• Manufacturer Part Number: PPC460EX-SUB800N
• Manufacturer: AMCC

460EX – PPC460EX Embedded Processor
Clocking Specifications
Table 19. Clocking Specifications
82
SysClk Input
Note: Input rising and falling edge slew rate ≥ 1V/ns
PLL VCO
Processor (CPU) Clock
MemClkOut and PLB Clock
OPB Clock
AHB Clock
Notes:
1. SysClk supports spread spectrum clocking with a -1% down-spread and a 40 kHz or less modulation frequency. For a 66.66 MHz
2. The modulation frequency of the input jitter should be lower than 100 kHz (to allow the PLL to track the jitter) or higher than 20 MHz (to
3. Slew rate is measured between 0.7V and 1.7V.
4. The maximum supported processor clock frequency for any part is specified in the part number (see “Ordering and PVR Information”
5. In order to support a 1-Gbps Ethernet data rate, the minimum OPB clock frequency is 66.66 MHz. If the Ethernet application is limited
Symbol
minimum SysClk, the modulation frequency range 66.00 MHz to 66.66 MHz is supported.
allow the PLL to filter the jitter). Within the frequency range 100 kHz to 20 MHz, the cycle to cycle jitter must be +/- 100 ps or less.
on page 5).
to 100 Mbps, the minimum OPB clock frequency is 33.33 MHz.
T
T
T
T
F
T
F
T
F
T
F
T
F
T
F
T
CS
CH
CH
CL
C
C
C
C
C
C
C
C
C
C
C
C
Frequency
Period
Edge stability (cycle-to-cycle jitter)
High time
Low time
Frequency
Period
Frequency
Period
Frequency
Period
High time
Frequency
Period
Frequency
Period
Parameter
40% of nominal period
40% of nominal period
45% of nominal period
133.33
66.66
66.66
66.66
0.50
1.00
Min
600
400
10
10
–
5
5
Preliminary Data Sheet
60% of nominal period
60% of nominal period
55% of nominal period
Revision 1.19 – June 17, 2009
2000
1000
Max
±0.1
1.66
100
200
100
200
2.5
7.5
15
15
15
AMCC Proprietary
Units
MHz
MHz
MHz
MHz
MHz
MHz
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Notes
1
2
3
4
5