PPC460EX-SUB800N AMCC, PPC460EX-SUB800N Datasheet - Page 96

• Manufacturer Part Number: PPC460EX-SUB800N
• Manufacturer: AMCC

460EX – PPC460EX Embedded Processor
DDR SDRAM Read Operation
The read of the incoming data from the SDRAM is done on the rising and falling edges of the differential DQS
signal. The data must be centered to these edges for correct operation.
DDR SDRAM Read Cycle Timing
The following diagram illustrates the relationship of the signals involved with a DDR read operation.
Figure 10. DDR SDRAM Memory Data and DQS
Table 29. I/O Timing—DDR SDRAM Read Timing T
1. T
2. MemClkOut frequency is 200MHz.
3. The time values in this table include 1/4 of a cycle at 200MHz (5ns x 0.25 = 1.25ns).
4. To obtain adjusted T
5. DDR1 is supported up to 200MHz. (400Mbps data rate).
96
MemData00:07
MemData08:15
MemData16:23
MemData24:31
MemData32:39
MemData40:47
MemData48:55
MemData56:63
ECC0:7
of the cycle time for the lower clock frequency (e.g., T
SD
and T
Signal Names
HD
are measured under worst case conditions.
SD
and T
MemData
HD
DQS
values for lower clock frequencies, subtract 0.75ns from the values in the table and add 1/4
Reference Signal
DQS0
DQS1
DQS2
DQS3
DQS4
DQS5
DQS6
DQS7
DQS8
T
T
SD
HD
SD
SD
− 1.25 + 0.25T
and T
Read Data vs DQS Set up
HD
for 200MHz
T
SD
0.393
0.388
0.397
0.396
0.394
0.395
0.393
0.394
0.389
CYC
(ns)
).
Preliminary Data Sheet
Revision 1.19 – June 17, 2009
Read Data vs DQS Hold
T
HD
0.311
0.314
0.307
0.309
0.291
0.291
0.295
0.308
0.306
(ns)
AMCC Proprietary