PPC460EX-SUB800N AMCC, PPC460EX-SUB800N Datasheet - Page 72

• Manufacturer Part Number: PPC460EX-SUB800N
• Manufacturer: AMCC

460EX – PPC460EX Embedded Processor
Table 9. Signal Functional Description (Part 9 of 10)
Notes:
1. Receiver input has hysteresis
2. Must pull up (recommended value is 3kΩ to OV
3. Must pull down (recommended value is 1kΩ to GND)
4. If not used, must pull up (recommended value is 3kΩ for LVTTL or 8.2kΩ for PCI to OV
5. If not used, must pull down (recommended value is 1kΩ)
6. Strapping input during reset; pull-up (recommended value is 3kΩ to OV
72
JTAG Interface
TCK
TDI
TDO
TMS
TRST
System Interface
SysClk
SysErr
SysReset
TmrClk
Halt
FSOURCE0
TestEn
GPIO00:21
GPIO22:63
TherMonA
TherMonB
Trace Interface
TrcBS0:2
TrcClk
TrcES0:4
TrcTS0:6
GND) required
Signal Name
Test Clock.
Test Data In.
Test Data Out.
Test Mode Select.
Test Reset. During chip power-up, this signal must be low from
the start of V
is stable in order to initialize the JTAG controller.
Main system clock input.
Set to 1 when a machine check is generated.
Main system reset. External logic can drive this pin low (minimum
of 32 SysClk cycles) to initiate a system reset. A system reset
can also be initiated by software.
Processor timer external input clock.
Halt from external debugger.
Reserved, Manufacturing Test Signal
Must connect to GND (no pull-down resistor required).
Test enable.
Note: Do not connect for normal operation.
General purpose I/O.
General purpose I/O.
On-chip thermal monitor (P diffusion).
On-chip thermal monitor (N diffusion).
Trace branch execution status.
Trace data capture clock; runs at 1/4 the frequency of the
processor.
Trace Execution Status is presented every fourth processor clock
cycle.
Additional information on trace execution and branch status.
DD
ramp-up until at least 32 SysClk cycles after V
DD
or 8.2kΩ for PCI to OV
Description
DD
DD
) or pull-down (recommended value is 1kΩ to
or equivalent.
Preliminary Data Sheet
DD
DD
Revision 1.19 – June 17, 2009
or equivalent.
I/O
I/O
I/O
O
O
O
O
O
O
O
I
I
I
I
I
I
I
I
I
I
I
3.3V tolerant
3.3V tolerant
3.3V tolerant
3.3V tolerant
3.3V LVTTL
3.3V LVTTL
3.3V LVTTL
3.3V LVTTL
3.3V LVTTL
2.5V CMOS
2.5V CMOS
2.5V CMOS
3.3V LVTTL
3.3V LVTTL
3.3V LVTTL
2.5V CMOS
3.3V LVTTL
3.3V LVTTL
3.3V LVTTL
3.3V LVTTL
w/pull-down
3.3V LVTTL
w/pull-up
w/pull-up
w/pull-up
w/pull-up
w/pull-up
w/pull-up
Thermal
monitor
Type
N/A
AMCC Proprietary
Notes
1, 2
1
5
1
1
1