PPC460EX-SUB800N AMCC, PPC460EX-SUB800N Datasheet - Page 92

• Manufacturer Part Number: PPC460EX-SUB800N
• Manufacturer: AMCC

460EX – PPC460EX Embedded Processor
2. The feedback trace can be made as short as possible such that MemDCFbdkD to MemDCFbdkR are directly
DDR I/O Characteristics
The DDR I/O operate as either 2.5V (SSTL2_25) DDR1 or 1.8V (SSTL_18) DDR2 receiver/drivers. The following
table lists the ODT termination supported, output driver impedance and input receiver capacitance.
Table 23. DDR I/O Characteristics
Table 24. DDR SDRAM Output Driver Specifications
92
MemData00:63
ECC0:7
DM0:8
MemClkOut
MemAddr00:14
BA0:2
RAS
CAS
WE
BankSel0:3
ClkEn0:3
DQS0:8/ DQS0:8
MemODT0:3
MemData00:63, ECC0:7, MemDCFdbkD, MemDCFdbkR,
MemAddr00:14, BA0:2, BankSel0:3, RAS, CAS, WE,
ClkEn0:3, DM0:8, MemODT0:3
DQS0:8/ DQS0:8
MemClkOut0:1/ MemClkOut0:1
Notes:
1. The output impedance (drive strength) for DQS0:8/ DQS0:8 and MemClkOut0:1/MemClkOut0:1 is programmable.
2. The 75-ohm internal termination for MemData00:63, DQS0:8/DQS0:8, and DM0:8 can be statically or dynamically enabled.
3. The 75-ohm internal termination is statically enabled for MemDCFdbkD, MemDCFdbkR, MemAddr00:14, BA0:2, BankSel0:3, RAS,
connected to one another. When using a short trace, software must calibrate the feedback timing using
MCIF0_RFDC[RFFD] . This method works well as long as the round trip flight time is less than half of a
MemClkOut cycle.
CAS, WE, ClkEn0:3, and MemODT0:3.
Signal Path
Signals
I/O H (maximum)
DDR2 ODT ( Ω )
10
10
10
10
10
10
10
10
10
10
10
10
10
75
75
–
Output Current (mA)
Output Impedance ( Ω )
18 or 36
18 or 36
36
Preliminary Data Sheet
Revision 1.19 – June 17, 2009
I/O L (maximum)
Input Capacitance (pF)
10
10
10
10
10
10
10
10
10
10
10
10
10
AMCC Proprietary
6.4
6.4
6.4