CY39200V388-125MGC Cypress Semiconductor Corp, CY39200V388-125MGC Datasheet
CY39200V388-125MGC
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CY39200V388-125MGC Summary of contents
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... Upper limit of typical gates is calculated by assuming only 10% of the channel memory is used. 2. Standby I values are with PLL not utilized, no output load and stable inputs. CC Cypress Semiconductor Corporation Document #: 38-03039 Rev. *D PRELIMINARY CPLDs at FPGA Densities™ — Clock polarity control at each register • ...
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Delta39K Speed Bins Device V CC 39K30 3.3/2.5 V 1.8 V 39K50 3.3/2.5 V 1.8 V 39K100 3.3/2.5 V 1.8 V 39K165 3.3/2.5 V 39K200 3.3/2.5 V 1.8 V Device Package Offering and I/O Count Including Dedicated Clock and ...
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GCLK[3:0] GCTL[3:0] PLL and Clock MUX 4 4 GCLK[3: Channel PIM RAM Cluster Cluster RAM RAM GCLK[3: ...
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All the members of the Delta39K family have Cypress’s highly regarded In-System Reprogrammability (ISR) feature, which simplifies both design and manufacturing flows, thereby reducing costs. The ISR feature provides the ability to recon- figure the devices without having design changes ...
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Logic Block (LB) The logic block is the basic building block of the Delta39K architecture. It consists of a product term array, an intelligent product-term allocator, and 16 macrocells. Product Term Array Each logic block features ...
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Macrocell Within each logic block there are 16 macrocells. Each macrocell accepts a sum product terms from the product term array. The sum of these 16 product terms can be output in either registered or combinatorial ...
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Embedded Memory Each member of the Delta39K family contains two types of embedded memory blocks. The channel memory block is placed at the intersection of horizontal and vertical routing channels. Each channel memory block is 4096 bits in size and ...
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Cluster PIM GCLK[3:0] The clocks for each port of the Dual-Port configuration are selected from four global clocks and two local clocks. One local clock is sourced from the horizontal channel and the other from the vertical channel. The ...
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In FIFO mode, the Write and Read ports are controlled by separate clock and enable signals. The clocks for each port are selected from four global clocks and ...
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The output buffer has a slew rate control option that can be used to configure the output for a slower slew rate. The input of the device and the ...
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Slew Rate Control The output buffer has a slew rate control option. This allows the output buffer to slew at a fast rate (3 V/ns slow rate (1 V/ns). All I/Os default to fast slew rate. For designs ...
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In general, PLLs are used to implement time-division- multiplex circuits to achieve higher performance with fewer device resources. For example, a system that operates on a 32-bit data path that runs at 40 MHz can be implemented with 16-bit ...
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Table 4. Recommended PLL Phase Shift Options Without External Feedback 0°,45°, 90°, 135°, 180°, 225°, 270°, 315° Table 5. Timing of Clock Phases for all Divide Options for a V Divide Period Factor (ns) Duty Cycle – ...
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GCLK[3: PIM MCS Cluster RAM GCLK[3: PIM Cluster RAM GCLK[3: PIM Cluster RAM ...
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Instruction Register TDI Bypass Reg. JTAG TMS TAP CONTROLLER Boundary Scan TCLK idcode Usercode ISR Prog. Data Registers Figure 11. JTAG Interface FLASH internal to the Delta39K package. Configuration is defined as the loading of a user’s design into the ...
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PRELIMINARY Maximum Ratings (Above which the useful life may be impaired. For user guide- lines, not tested.) Storage Temperature (39k200, 208 EQFP) – +125 C Storage Temperature (all other densities & packages)....... .......... – +150 C ...
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Capacitance Parameter Description C Input/Output Capacitance I/O C Clock Signal Capacitance CLK C PCI Compliant PCI [9] DC Characteristics (I/ REF CCIO I/O Standards (V) ( LVTTL –2mA N/A 3.3 –2 mA LVTTL –4mA 3.3 ...
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Power-up Sequence Requirements • Upon power-up, all the outputs remain three-stated until all the V pins have powered-up to the nominal voltage and CC the part has completed configuration. • The part will not start configuration until ...
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Switching Characteristics — Parameter Descriptions Parameter Product Term Clock t Set-up time for macrocell used as input register, from input to product term clock MCSPT t Hold time of macrocell used as an input register MCHPT t Product term clock ...
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Cluster Memory Timing Parameter Descriptions Parameter Asynchronous Mode Parameters t Cluster memory access time. Delay from address change to Read data out CLMAA t Write Enable pulse width CLMPWE t Address set-up to the beginning of Write Enable with both ...
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Channel Memory Timing Parameter Descriptions Parameter Dual Port Asynchronous Mode Parameters t Channel memory access time. Delay from address change to Read data out CHMAA t Write enable pulse width CHMPWE t Address set-up to the beginning of Write enable ...
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Switching Characteristics — Parameter Values 233 Parameter Min. Max. Combinatorial Mode Parameters 6.0 PRR t 9.5 PRO t 3.3 PRW Synchronous Clocking Parameters t 2.7 MCS t 0 MCH t ...
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Switching Characteristics — Parameter Values 233 Parameter Min. Max. PLL Parameters t –150 150 MCCJ t –1.35 –0.85 DWSA t –150 150 DWOSA t 250 LOCK INDUTY [14] f 6.2 266 PLLO [14] f 12.5 133 PLLI ...
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Input and Output Standard Timing Delay Adjustments All the timing specifications in this data sheet are specified based on LVCMOS compliant inputs and outputs (fast slew rates). Apply following adjustments if the inputs and outputs are configured to operate at ...
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Cluster Memory Timing Parameter Values 233 Parameter Min. Max. Asynchronous Mode Parameters t 10.2 CLMAA t 5.5 CLMPWE t 1.8 CLMSA t 0.9 CLMHA t 5.5 CLMSD t 0.4 CLMHD Synchronous Mode Parameters t 9.5 CLMCYC1 t 5.0 CLMCYC2 t ...
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Channel Memory Timing Parameter Values 233 Parameter Min. Max. Dual-Port Asynchronous Mode Parameters t 10 CHMAA t 5.5 CHMPWE t 1.8 CHMSA t 0.9 CHMHA t 5.5 CHMSD t 0.4 CHMHD t 8.5 CHMBA Dual-Port Synchronous Mode Parameters t 9.5 ...
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Switching Waveforms Combinatorial Output INPUT COMBINATORIAL OUTPUT Registered Output with Synchronous Clocking (Macrocell) INPUT SYNCHRONOUS CLOCK REGISTERED OUTPUT Registered Input in I/O Cell DATA INPUT INPUT REGISTER CLOCK REGISTERED OUTPUT Document #: 38-03039 Rev. *D PRELIMINARY MCS ...
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Switching Waveforms (continued) Clock to Clock INPUT REGISTER CLOCK MACROCELL REGISTER CLOCK PT Clock to PT Clock DATA INPUT PT CLOCK Asynchronous Reset/Preset RESET/PRESET INPUT REGISTERED OUTPUT CLOCK Output Enable/Disable GLOBAL CONTROL INPUT OUTPUTS Document #: 38-03039 Rev. *D PRELIMINARY ...
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Switching Waveforms (continued) Cluster Memory Asynchronous Timing ADDRESS (AT THE CLUSTER INPUT) WRITE ENABLE INPUT t CLMCLAA OUTPUT Cluster Memory Asynchronous Timing 2 ADDRESS (AT THE I/O PIN) WRITE ENABLE INPUT OUTPUT Document #: 38-03039 Rev. *D PRELIMINARY READ READ ...
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Switching Waveforms (continued) Cluster Memory Synchronous Flow-Through Timing GLOBAL CLOCK t t CLMS CLMH ADDRESS WRITE ENABLE REGISTERED INPUT t CLMDV1 REGISTERED OUTPUT Cluster Memory Internal Clocking MACROCELL INPUT CLOCK CLUSTER MEMORY INPUT CLOCK CLUSTER MEMORY OUTPUT CLOCK Document #: ...
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Switching Waveforms (continued) Cluster Memory Output Register Timing (Asynchronous Inputs) ADDRESS WRITE ENABLE INPUT GLOBAL CLOCK (OUTPUT REGISTER) REGISTERED OUTPUT Cluster Memory Output Register Timing (Synchronous Inputs) ADDRESS WRITE ENABLE INPUT GLOBAL CLOCK (INPUT REGISTER) GLOBAL CLOCK (OUTPUT REGISTER) REGISTERED ...
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Switching Waveforms (continued) Channel Memory DP Asynchronous Timing ADDRESS A n-1 WRITE ENABLE DATA INPUT OUTPUT D n–1 Channel Memory Internal Clocking MACROCELL INPUT CLOCK CHANNEL MEMORY INPUT CLOCK CHANNEL MEMORY OUTPUT CLOCK Document #: 38-03039 Rev. *D PRELIMINARY A ...
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Switching Waveforms (continued) Channel Memory Internal Clocking 2 MACROCELL INPUT CLOCK FIFO READ CLOCK FIFO WRITE CLOCK FIFO READ OR WRITE CLOCK Channel Memory DP SRAM Flow-Through R/W Timing CLOCK t CHMS A ADDRESS n–1 WRITE ENABLE DATA D n–1 ...
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Switching Waveforms (continued) Channel Memory DP SRAM Pipeline R/W Timing CLOCK A ADDRESS n–1 WRITE ENABLE DATA D n–1 INPUT OUTPUT Dual-Port Asynchronous Address Match Busy Signal B ADDRESS ADDRESS B n–1 ADDRESS MATCH Document #: 38-03039 ...
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Switching Waveforms (continued) Dual-Port Synchronous Address Match Busy Signal CLOCK A ADDRESS A n–1 B ADDRESS B n–1 ADDRESS MATCH Document #: 38-03039 Rev. *D PRELIMINARY CHMS t CHMBDV Delta39K™ ISR™ CPLD Family B n+1 ...
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Switching Waveforms (continued) Channel Memory Synchronous FIFO Empty/Write Timing PORT B CLOCK WRITE ENABLE REGISTERED INPUT EMPTY FLAG (Active LOW) PORT A CLOCK READ ENABLE RE REGISTERED OUTPUT Document #: 38-03039 Rev. *D PRELIMINARY t CHMCLK t t CHMFS CHMFH ...
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Switching Waveforms (continued) Channel Memory Synchronous FIFO Full/Read Timing PORT A CLOCK READ ENABLE REGISTERED OUTPUT FULL FLAG (Active LOW) PORT B CLOCK WRITE ENABLE REGISTERED INPUT Document #: 38-03039 Rev. *D PRELIMINARY t t CHMFS CHMFH t CHMFRDV t ...
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Switching Waveforms (continued) Channel Memory Synchronous FIFO Programmable Flag Timing PORT B CLOCK WRITE ENABLE PROGRAMMABLE ALMOST EMPTY FLAG (active LOW) PORT A CLOCK READ ENABLE PORT B CLOCK WRITE ENABLE t CHMFO PROGRAMMABLE ALMOST FULL FLAG (Active LOW) PORT ...
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Switching Waveforms (continued) Channel Memory Synchronous FIFO Master Reset Timing t MASTER RESET INPUT READ ENABLE / WRITE ENABLE t CHMFRSF EMPTY/FULL PROGRAMMABLE ALMOST EMPTY FLAGS t CHMFRSF HALF-FULL/ PROGRAMMABLE ALMOST FULL FLAGS t CHMFRSF REGISTERED OUTPUT ...
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Delta39K Part Numbers (Ordering Information) Speed Device (MHz) Ordering Code 39K30 233 CY39030V208-233NTC CY39030V256-233BBC CY39030V256-233MBC 125 CY39030V208-125NTC CY39030V256-125BBC CY39030V256-125MBC CY39030Z208-125NC CY39030Z256-125BBC CY39030Z256-125MBC CY39030V208-125NTI CY39030V256-125BBI CY39030Z256-125BBI CY39030Z208-125NI 83 CY39030V208-83NTC CY39030V256-83BBC CY39030V256-83MBC CY39030Z256-83MBC CY39030Z208-83NC CY39030Z256-83BBC CY39030V208-83NTI CY39030V256-83BBI CY39030Z256-83BBI CY39030Z208-83NI 39K50 233 ...
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Delta39K Part Numbers (Ordering Information) Speed Device (MHz) Ordering Code 39K50 125 CY39050V208-125NTI CY39050V256-125BBI CY39050Z256-125BBI CY39050Z208-125NI 83 CY39050V208-83NTC CY39050V256-83BBC CY39050V388-83MGC CY39050V484-83MBC CY39050Z208-83NC CY39050Z484-83MBC CY39050Z256-83BBC CY39050Z388-83MGC CY39050V208-83NTI CY39050V256-83BBI CY39050Z256-83BBI CY39050Z208-83NI 39K100 200 CY39100V208B-200NTC CY39100V256B-200BBC CY39100V484B-200BBC CY39100V388B-200MGC CY39100V676B-200MBC Document #: 38-03039 Rev. ...
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Delta39K Part Numbers (Ordering Information) Speed Device (MHz) Ordering Code 39K100 125 CY39100V208B-125NTC CY39100V256B-125BBC CY39100V484B-125BBC CY39100V388B-125MGC CY39100V676B-125MBC CY39100Z208-125NC CY39100Z256-125BBC CY39100Z484-125BBC CY39100Z388-125MGC CY39100Z676-125MBC CY39100V208B-125NTI CY39100V256B-125BBI CY39100V484B-125BBI CY39100Z208B-125NI CY39100Z256B-125BBI CY39100Z484B-125BBI 83 CY39100V208B-83NTC CY39100V256B-83BBC CY39100V484B-83BBC CY39100V388B-83MGC CY39100V676B-83MBC CY39100Z208-83NC CY39100Z256-83BBC CY39100Z484-83BBC CY39100Z388-83MGC CY39100Z676-83MBC CY39100V208B-83NTI ...
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Delta39K Part Numbers (Ordering Information) Speed Device (MHz) Ordering Code 39K165 181 CY39165V208-181NTC CY39165V484-181BBC CY39165V388-181MGC CY39165V676-181MBC 125 CY39165V208-125NTC CY39165V484-125BBC CY39165V388-125MGC CY39165V676-125MBC CY39165V208-125NTI CY39165V484-125BBI 83 CY39165V208-83NTC CY39165V484-83BBC CY39165V388-83MGC CY39165V676-83MBC CY39165V208-83NTI CY39165V484-83BBI Document #: 38-03039 Rev. *D PRELIMINARY (continued) Package Name NT208 ...
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... Delta39K Part Numbers (Ordering Information) Speed Device (MHz) Ordering Code 39K200 181 CY39200V208-181NTC CY39200V484-181BBC CY39200V388-181MGC CY39200V676-181MBC 125 CY39200V208-125NTC CY39200V484-125BBC CY39200V388-125MGC CY39200V676-125MBC CY39200Z208-125NTC CY39200Z484-125BBC CY39200Z388-125MGC CY39200Z676-125MBC CY39200V208-125NTI CY39200V484-125BBI CY39200Z208-125NTI CY39200Z484-125BBI 83 CY39200V208-83NTC CY39200V484-83BBC CY39200V388-83MGC CY39200V676-83MBC CY39200Z208-83NTC CY39200Z484-83BBC CY39200Z388-83MGC CY39200Z676-83MBC CY39200V208-83NTI CY39200V484-83BBI CY39200Z208-83NTI CY39200Z484-83BBI Document #: 38-03039 Rev ...
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CPLD Boot EEPROM Part Numbers (Ordering Information) Speed Device (MHz) 2Mbit 15 CY3LV002-10JC 10 CY3LV002-10JC 1Mbit 15 CY3LV010-10JC 10 CY3LV010-10JI 512Kbit 15 CY3LV512-10JC 10 CY3LV512-10JI Recommended CPLD Boot EEPROM for corresponding Delta39K CPLDs CPLD Device 39K30 39K50 39K100 39K165 ...
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Package Diagrams 208-Lead Enhanced Quad Flat Pack (EQFP) NT208 Document #: 38-03039 Rev. *D PRELIMINARY 208-Lead Plastic Quad Flatpack (PQFP) N208 Delta39K™ ISR™ CPLD Family 51-85069-B Page ...
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Package Diagrams (continued) Document #: 38-03039 Rev. *D PRELIMINARY 388-Lead Ball Grid Array MG388 Delta39K™ ISR™ CPLD Family 51-85103-*B Page ...
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Package Diagrams (continued) 256-Ball Thin Ball Grid Array (17 × 17 × 1.6 mm) BB256/MB256 Document #: 38-03039 Rev. *D PRELIMINARY Delta39K™ ISR™ CPLD Family 51-85108-*B Page ...
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Package Diagrams (continued) 484-Ball Thin Ball Grid Array (23 × 23 × 1.6 mm) BB484/MB484 Document #: 38-03039 Rev. *D PRELIMINARY Delta39K™ ISR™ CPLD Family 51-85124-*A Page ...
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Package Diagrams (continued) Document #: 38-03039 Rev. *D PRELIMINARY 676-Ball FBGA (27 × 27 × 1.6 mm) BB676 Delta39K™ ISR™ CPLD Family 51-85125-*A Page ...
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Pin Tables Table 6. Pin Definition Table Pin Name Function GCLK0-3 Input GCTL0-3 Input GND Ground IO/V Input/Output REF0 IO/V Input/Output REF1 IO/V Input/Output REF2 IO/V Input/Output REF3 IO/V Input/Output REF4 IO/V Input/Output REF5 IO/V Input/Output REF6 IO/V Input/Output REF7 ...
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Table 7. Mode Select (MSEL) Pin Connectivity Table GND Delta39K - Self-Boot™ Solution V Delta39K - with external boot PROM CCCNFG Table 8. 208 EQFP/PQFP Pin Table Pin CY39030 1 GCTL0 2 GND 3 GCLK0 4 GND 5 IO0 6 ...
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Table 8. 208 EQFP/PQFP Pin Table (continued) Pin CY39030 40 IO/V REF1 41 IO1 42 IO1 43 IO1 44 IO1 45 V CCPRG 46 V CCIO1 47 GND 48 IO1 49 IO/V REF1 50 IO1 51 IO1 52 V CCCNFG ...
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Table 8. 208 EQFP/PQFP Pin Table (continued) Pin CY39030 84 V CCIO2 85 V CCIO3 [19] 86 IO3 [19] 87 IO3 [19] 88 IO/V REF3 89 V CCIO3 90 GND 91 IO3 92 IO3 93 IO3 94 IO3 95 IO3 ...
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Table 8. 208 EQFP/PQFP Pin Table (continued) Pin CY39030 128 GND 129 NC 130 NC 131 V CCIO4 132 V CCIO5 [19] 133 IO5 [19] 134 IO5 [19] 135 IO/V REF5 136 IO5 137 IO5 138 V CCIO5 139 IO5 ...
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Table 8. 208 EQFP/PQFP Pin Table (continued) Pin CY39030 172 IO6 173 IO/V REF6 174 IO6 175 IO6 176 IO6 177 GND 178 V CCIO6 179 V CCPLL 180 GND 181 V CC 182 GND [19] 183 IO/V REF6 [19] ...
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Table 9. 388 BGA Pin Table Pin CY39050 A1 GND IO7 A4 IO7 A5 IO7 A6 IO7 A7 IO7 IO7 A10 IO7 A11 IO/V REF7 A12 IO7 [19] A13 IO7 [19] A14 IO6 A15 ...
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Table 9. 388 BGA Pin Table (continued) Pin CY39050 B18 IO6 B19 IO6 B20 IO/VREF6 B21 IO6 B22 NC B23 NC B24 IO6 B25 IO6 B26 IO6 C1 IO0 C2 IO/V REF7 IO7 C5 IO7 C6 NC ...
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Table 9. 388 BGA Pin Table (continued) Pin CY39050 D10 V CCIO7 D11 IO7 D12 V CCIO7 D13 V CC D14 V CCIO6 D15 V CCIO6 D16 IO6 D17 V CCPLL D18 V CCIO6 D19 V CCIO6 D20 GCLK2 D21 ...
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Table 9. 388 BGA Pin Table (continued) Pin CY39050 H4 V CCIO0 H23 V CCJTAG H24 IO5 H25 IO5 H26 IO5 CCIO0 J23 V CCIO5 J24 NC J25 IO5 J26 IO5 K1 ...
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Table 9. 388 BGA Pin Table (continued) Pin CY39050 M16 GND M23 V CCIO5 M24 NC M25 NC M26 IO/V REF0 [19] N3 IO0 [19] N4 IO1 N11 GND N12 GND N13 GND N14 GND N15 ...
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Table 9. 388 BGA Pin Table (continued) Pin CY39050 [19] R24 IO4 [19] R25 IO4 R26 T11 GND T12 GND T13 GND T14 GND T15 GND T16 GND [19] T23 IO4 ...
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Table 9. 388 BGA Pin Table (continued) Pin CY39050 Y4 IO1 Y23 NC Y24 NC Y25 NC Y26 IO4 AA1 IO1 AA2 IO1 AA3 IO/V REF1 AA4 IO1 AA23 IO4 AA24 IO4 AA25 IO/V REF4 AA26 IO4 AB1 V CCCNFG ...
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Table 9. 388 BGA Pin Table (continued) Pin CY39050 AC24 IO4 AC25 IO4 AC26 IO4 AD1 Reset AD2 CCLK AD3 IO/V REF2 AD4 IO2 AD5 IO/V REF2 AD6 IO2 AD7 NC AD8 NC AD9 IO2 AD10 IO/V REF2 AD11 IO2 ...
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Table 9. 388 BGA Pin Table (continued) Pin CY39050 AE16 IO3 AE17 IO3 AE18 IO3 AE19 IO3 AE20 IO/V REF3 AE21 NC AE22 IO3 AE23 NC AE24 NC AE25 IO3 AE26 IO3 AF1 GND AF2 IO2 AF3 IO2 AF4 IO2 ...
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Table 10. 256 FBGA Pin Table Pin CY39030 A1 GND IO IO6/Lock A9 A10 IO/V A11 IO/V A12 A13 A14 A15 A16 GND B1 B2 GND IO/V ...
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Table 10. 256 FBGA Pin Table (continued) Pin CY39030 C12 C13 C14 GND C15 C16 GND D5 D6 IO/V D7 [19] D8 [19] D9 D10 D11 IO/V D12 D13 GND D14 TCLK D15 D16 E1 E2 ...
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Table 10. 256 FBGA Pin Table (continued) Pin CY39030 F8 GCLK3 F9 GCTL2 F10 GCLK2 F11 F12 F13 IO/V F14 V F15 V CCJTAG F16 IO GCTL0 G7 GND G8 GND G9 GND ...
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Table 10. 256 FBGA Pin Table (continued) Pin CY39030 [19] J4 [19 GND J8 GND J9 GND J10 GND J11 [19] J12 [19] J13 [19] J14 J15 J16 CCPRG IO/V K5 ...
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Table 10. 256 FBGA Pin Table (continued) Pin CY39030 L16 Data M5 Reconfig M6 M7 [19] M8 [19] M9 M10 M11 M12 M13 M14 M15 M16 N1 IO GND N5 MSEL N6 IO/V ...
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Table 10. 256 FBGA Pin Table (continued) Pin CY39030 P12 P13 P14 GND P15 P16 R1 R2 GND R3 CCLK CCCNFG R10 R11 V R12 R13 R14 R15 GND R16 T1 GND ...
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Table 11. 484 FBGA Pin Table Pin CY39050 A1 GND A2 GND IO7 A6 IO7 IO7 A9 IO7 A10 IO7 A11 GND A12 GND A13 IO6 A14 IO6 A15 IO6 A16 NC ...
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Table 11. 484 FBGA Pin Table (continued) Pin CY39050 IO7 IO7 C9 IO7 C10 IO/ VREF7 C11 IO7 C12 IO6 C13 NC C14 IO6 C15 IO6 C16 NC ...
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Table 11. 484 FBGA Pin Table (continued) Pin CY39050 IO0 E5 GND E6 IO7 E7 IO7 E8 IO7 E9 V CCIO7 E10 V CC E11 IO/V REF7 E12 NC E13 V CCPLL E14 V CCIO6 E15 NC ...
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Table 11. 484 FBGA Pin Table (continued) Pin CY39050 G4 IO0 G5 IO0 G6 IO0 G7 GND G8 IO7 G9 NC G10 IO7 [19] G11 IO7 [19] G12 IO6 G13 IO6 G14 IO/V REF6 G15 IO6 G16 GND G17 TCLK ...
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Table 11. 484 FBGA Pin Table (continued) Pin CY39050 CCIO0 J7 IO/V REF0 IO7 J10 GCTL3 J11 GCLK3 J12 GCTL2 J13 GCLK2 J14 IO5 J15 IO5 J16 IO/V REF5 J17 V CCIO5 J18 ...
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Table 11. 484 FBGA Pin Table (continued) Pin CY39050 [19] L6 IO0 L7 IO/V REF0 GCLK0 L10 GND L11 GND L12 GND L13 GND L14 GCLK1 L15 NC L16 IO/V REF5 [19] L17 IO5 [19] L18 IO5 ...
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Table 11. 484 FBGA Pin Table (continued) Pin CY39050 N7 IO/V REF1 N10 GND N11 GND N12 GND N13 GND N14 NC N15 IO4 N16 IO/V REF4 N17 V CCIO4 N18 V CCPRG N19 NC N20 ...
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Table 11. 484 FBGA Pin Table (continued) Pin CY39050 R8 Reconfig R9 IO2 R10 IO2 [19] R11 IO2 [19] R12 IO3 R13 IO3 R14 IO3 R15 NC R16 NC R17 NC R18 NC R19 IO4 R20 IO4 R21 IO4 R22 ...
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Table 11. 484 FBGA Pin Table (continued) Pin CY39050 U9 V CCIO2 U10 V CCIO2 U11 IO2 U12 IO2 U13 V CCIO3 U14 V CCIO3 U15 IO3 U16 IO3 U17 GND U18 IO4 U19 IO4 U20 IO4 U21 IO4 U22 ...
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Table 11. 484 FBGA Pin Table (continued) Pin CY39050 W10 NC W11 IO2 W12 IO2 W13 NC W14 NC W15 IO3 W16 IO3 W17 IO3 W18 NC W19 GND W20 NC W21 V CCIO4 W22 ...
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Table 11. 484 FBGA Pin Table (continued) Pin CY39050 AA11 IO2 AA12 IO3 AA13 IO3 AA14 NC AA15 IO3 AA16 NC AA17 NC AA18 IO/V REF3 AA19 V CCIO3 AA20 NC AA21 GND AA22 GND AB1 GND AB2 GND AB3 ...
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Table 12. 676 FBGA Pin Table Pin CY39100 CY39165 A1 GND GND IO7 A4 NC IO7 A5 NC IO7 CCIO7 A7 NC IO7 A8 NC IO7 A9 NC IO7 A10 NC NC ...
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Table 12. 676 FBGA Pin Table (continued) Pin CY39100 CY39165 D11 NC V CCIO7 D12 IO7 IO7 D13 IO7 IO7 D14 IO6 IO6 D15 IO6 IO6 D16 NC V CCIO6 D17 IO/V IO/V REF6 REF6 [20] D18 IO6 IO6 D19 ...
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Table 12. 676 FBGA Pin Table (continued) Pin CY39100 CY39165 G21 TDO TDO G22 NC IO5 G23 NC IO5 G24 NC IO5 G25 NC NC G26 IO0 H4 IO0 IO0 ...
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Table 12. 676 FBGA Pin Table (continued) Pin CY39100 CY39165 L5 IO/V IO/V REF0 REF0 L6 IO0 IO0 CCIO0 CCIO0 L9 IO/V IO/V REF0 REF0 L10 IO0 IO0 L11 IO7 IO7 L12 ...
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Table 12. 676 FBGA Pin Table (continued) Pin CY39100 CY39165 P15 GND GND P16 IO4 IO4 [19] P17 IO4 IO4 [19] P18 IO4 IO4 [19] P19 IO4 IO4 P20 IO5 IO5 P21 IO5 IO5 P22 IO4 IO4 P23 IO4 IO4 ...
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Table 12. 676 FBGA Pin Table (continued) Pin CY39100 CY39165 U25 NC NC U26 IO1 V4 IO1 IO1 V5 IO1 IO1 V6 IO/V IO/V REF1 REF1 V7 IO1 IO1 V8 ...
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Table 12. 676 FBGA Pin Table (continued) Pin CY39100 CY39165 AA9 IO2 IO2 AA10 IO2 IO2 AA11 IO/V IO/V REF2 REF2 AA12 IO/V IO/V REF2 REF2 AA13 IO2 IO2 AA14 IO2 IO2 AA15 IO/V IO/V REF3 REF3 AA16 IO/V IO/V ...
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... Document #: 38-03039 Rev. *D © Cypress Semiconductor Corporation, 2002. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a Cypress Semiconductor product. Nor does it convey or imply any license under patent or other rights. Cypress Semiconductor does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user ...
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Document Title: DELTA39K™ ISR™ CPLD FAMILY Document Number: 38-03039 Issue REV. ECN NO. Date ** 106503 05/30/01 *A 107625 07/11/01 *B 109681 11/16/01 *C 112376 12/21/01 *D 112946 04/04/02 Document #: 38-03039 Rev. *D PRELIMINARY Orig. of Change SZV Change ...