CY39200V388-125MGC Cypress Semiconductor Corp, CY39200V388-125MGC Datasheet - Page 4

• Manufacturer Part Number: CY39200V388-125MGC
• Description: IC CPLD 200K GATE 388-BGA
• Manufacturer: Cypress Semiconductor Corp
• Series: Delta 39K™ ISR™r

Specifications of CY39200V388-125MGC

• Programmable Type: In-System Reprogrammable™ (ISR™) Flash
• Delay Time Tpd(1) Max: 10.0ns
• Voltage Supply - Internal: 2.5V, 3.3V
• Number Of Macrocells: 3072
• Number Of Gates: 288000
• Number Of I /o: 294
• Operating Temperature: 0°C ~ 70°C
• Mounting Type: Surface Mount
• Package / Case: 388-BGA
• Voltage: 1.8V, 2.5V, 3.3V
• Memory Type: FLASH
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Features: -
• Number Of Logic Elements/cells: -
• Other names: 428-1297

All the members of the Delta39K family have Cypress’s highly
regarded In-System Reprogrammability (ISR) feature, which
simplifies both design and manufacturing flows, thereby
reducing costs. The ISR feature provides the ability to recon-
figure the devices without having design changes cause
pinout or timing changes in most cases. The Cypress ISR
function is implemented through a JTAG-compliant serial
interface. Data is shifted in and out through the TDI and TDO
pins respectively. Superior routability, simple timing, and the
ISR allows users to change existing logic designs while simul-
taneously fixing pinout assignments and maintaining system
performance.
The entire family features JTAG for ISR and boundary scan,
and is compatible with the PCI Local Bus specification,
meeting the electrical and timing requirements. The Delta39K
family also features user programmable bus-hold and slew
rate control capabilities on each I/O pin.
AnyVolt Interface
All Delta39KV devices feature an on-chip regulator, which
accepts 3.3V or 2.5V on the V
to 1.8V internally, the voltage level at which the core operates.
The Delta39KZ devices accept 1.8V on the V
directly. With Delta39K’s AnyVolt technology, the I/O pins can
be connected to either 1.8V, 2.5V, or 3.3V. All Delta39K
devices are 3.3V tolerant regardless of V
Note:
Document #: 38-03039 Rev. *D
5.
Device
39KV
39KZ
For HSTL only.
3.3V or 2.5V
1.8V
V
CC
3.3V or 2.5V or 1.8V or 1.5V
3.3V or 2.5V or 1.8V or 1.5V
CC
supply pins and steps it down
PRELIMINARY
Pin inputs from the I/O cells
drive dedicated tracks in the
horizontal and vertical routing
channels
CCIO
V
CCIO
Memory
Cluster
Block
LB
LB
LB
LB
Figure 2. Delta39K Routing Interface
or V
CC
72
Cluster
CC
supply pins
PIM
64
settings.
Memory
Cluster
Block
LB
LB
LB
LB
[5]
[5]
Channel
Memory
Block
72
64
Global Routing Description
The routing architecture of the Delta39K is made up of
horizontal and vertical (H and V) routing channels. These
routing channels allow signals from each of the Delta39K
architectural components to communicate with one another. In
addition to the horizontal and vertical routing channels that
interconnect the I/O banks, channel memory blocks, and logic
block clusters, each LBC contains a Programmable Inter-
connect Matrix (PIM™), which is used to route signals among
the logic blocks and the cluster memory blocks.
Figure 2 is a block diagram of the routing channels that
interface within the Delta39K architecture. The LBC is exactly
the same for every member of the Delta39K CPLD family.
Logic Block Cluster (LBC)
The Delta39K architecture consists of several logic block
clusters, each of which have eight Logic Blocks (LB) and two
cluster memory blocks connected via a Programmable Inter-
connect Matrix (PIM) as shown in Figure 3. Each cluster
memory block consists of 8-Kbit single-port RAM, which is
configurable as synchronous or asynchronous. The cluster
memory blocks can be cascaded with other cluster memory
blocks within the same LBC as well as other LBCs to
implement larger memory functions. If a cluster memory block
is not specifically utilized by the designer, Cypress’s Warp
software can automatically use it to implement large blocks of
logic.
All LBCs interface with each other via horizontal and vertical
routing channels.
I/O Block
V-to-H
PIM
Channel memory
outputs drive
dedicated tracks in the
horizontal and vertical
routing channels
H-to-V
PIM
Delta39K™ ISR™
CPLD Family
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