CY39200V388-125MGC Cypress Semiconductor Corp, CY39200V388-125MGC Datasheet - Page 14

• Manufacturer Part Number: CY39200V388-125MGC
• Description: IC CPLD 200K GATE 388-BGA
• Manufacturer: Cypress Semiconductor Corp
• Series: Delta 39K™ ISR™r

Specifications of CY39200V388-125MGC

• Programmable Type: In-System Reprogrammable™ (ISR™) Flash
• Delay Time Tpd(1) Max: 10.0ns
• Voltage Supply - Internal: 2.5V, 3.3V
• Number Of Macrocells: 3072
• Number Of Gates: 288000
• Number Of I /o: 294
• Operating Temperature: 0°C ~ 70°C
• Mounting Type: Surface Mount
• Package / Case: 388-BGA
• Voltage: 1.8V, 2.5V, 3.3V
• Memory Type: FLASH
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Features: -
• Number Of Logic Elements/cells: -
• Other names: 428-1297

IEEE 1149.1-compliant JTAG Operation
The Delta39K family has an IEEE 1149.1 JTAG interface for
both Boundary Scan and ISR operations.
Four dedicated pins are reserved on each device for use by
the Test Access Port (TAP).
Boundary Scan
The Delta39K family supports Bypass, Sample/Preload,
Extest, Intest, Idcode and Usercode boundary scan instruc-
tions. The JTAG interface is shown in Figure 11.
In-System Reprogramming (ISR)
In-System Reprogramming is the combination of the capability
to program or reprogram a device on-board, and the ability to
support design changes without changing the system timing
or device pinout. This combination means design changes
Document #: 38-03039 Rev. *D
t
PD
t
MCS
t
GCLK[3:0]
GCLK[3:0]
GCLK[3:0]
MCCO
Cluster
Cluster
Cluster
LB 0
LB 1
LB 2
LB 3
RAM
LB 0
LB 1
LB 2
LB 3
RAM
LB 0
LB 1
LB 2
LB 3
RAM
PIM
PIM
PIM
Cluster
Cluster
Cluster
PRELIMINARY
RAM
LB 7
LB 6
LB 5
LB 4
RAM
LB 7
LB 6
LB 5
LB 4
LB 7
LB 6
LB 5
LB 4
RAM
4
4
4
Figure 10. Timing Model for 39K100 Device
Channel
Channel
Channel
RAM
RAM
RAM
t
Cluster
Cluster
Cluster
SCS
LB 0
LB 1
LB 2
LB 3
RAM
LB 0
LB 1
LB 2
LB 3
RAM
LB 0
LB 1
LB 2
LB 3
RAM
PIM
PIM
PIM
Cluster
Cluster
Cluster
RAM
LB 7
LB 6
LB 5
LB 4
RAM
LB 7
LB 6
LB 5
LB 4
LB 7
LB 6
LB 5
LB 4
RAM
4
4
4
Channel
Channel
Channel
during debug or field upgrades do not cause board respins.
The Delta39K family implements ISR by providing a JTAG
compliant interface for on-board programming, robust routing
resources for pinout flexibility, and a simple timing model for
consistent system performance.
Configuration
Each device of the Delta39K family is available in a volatile and
a Self-Boot package. Cypress’s CPLD boot EEPROM is used
to store configuration data for the volatile solution and an
embedded on-chip FLASH memory device is used for the Self-
Boot solution.
For volatile Delta39K packages, programming is defined as
the loading of a user’s design into the external CPLD boot
EEPROM. For Self-Boot Delta39K packages, programming is
defined as the loading of a user’s design into the on-chip
RAM
RAM
RAM
Cluster
Cluster
Cluster
LB 0
LB 1
LB 2
LB 3
RAM
LB 0
LB 1
LB 2
LB 3
RAM
LB 0
LB 1
LB 2
LB 3
RAM
PIM
PIM
PIM
Cluster
Cluster
Cluster
LB 7
LB 6
LB 5
LB 4
RAM
RAM
LB 7
LB 6
LB 5
LB 4
RAM
LB 7
LB 6
LB 5
LB 4
4
4
4
Channel
Channel
Channel
RAM
RAM
RAM
Delta39K™ ISR™
Cluster
Cluster
LB 0
LB 1
LB 2
LB 3
SRAM
LB 0
LB 1
LB 2
LB 3
RAM
LB 0
LB 1
LB 2
LB 3
RAM
8 Kb
PIM
PIM
PIM
CPLD Family
Cluster
Cluster
RAM
LB 7
LB 6
LB 5
LB 4
SRAM
LB 7
LB 6
LB 5
LB 4
LB 7
LB 6
LB 5
LB 4
RAM
8 Kb
4
4
4
Channel
Channel
Channel
RAM
RAM
RAM
Page 14 of 91
t
SCS2