CY39200V388-125MGC Cypress Semiconductor Corp, CY39200V388-125MGC Datasheet - Page 91

• Manufacturer Part Number: CY39200V388-125MGC
• Description: IC CPLD 200K GATE 388-BGA
• Manufacturer: Cypress Semiconductor Corp
• Series: Delta 39K™ ISR™r

Specifications of CY39200V388-125MGC

• Programmable Type: In-System Reprogrammable™ (ISR™) Flash
• Delay Time Tpd(1) Max: 10.0ns
• Voltage Supply - Internal: 2.5V, 3.3V
• Number Of Macrocells: 3072
• Number Of Gates: 288000
• Number Of I /o: 294
• Operating Temperature: 0°C ~ 70°C
• Mounting Type: Surface Mount
• Package / Case: 388-BGA
• Voltage: 1.8V, 2.5V, 3.3V
• Memory Type: FLASH
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Features: -
• Number Of Logic Elements/cells: -
• Other names: 428-1297

Document #: 38-03039 Rev. *D
Document Title: DELTA39K™ ISR™ CPLD FAMILY
Document Number: 38-03039
REV.
*A
*B
*C
*D
**
ECN NO.
106503
107625
109681
112376
112946
05/30/01
11/16/01
12/21/01
04/04/02
07/11/01
Issue
Date
PRELIMINARY
Change
Orig. of
SZV
RN
RN
RN
RN
Change from Spec #: 38-00830 to 38-03039
Deleted 39K15 device and the associate -250 MHz bin specs.
Deleted 144FBGA package and associated part numbers.
Changed ESD spec from “MIL-STD-883” to “JEDEC EIA./JESD22-A114-A
“.
Changed the Prime bin for 39K50 and 39K30 from “MHz” to “233 MHz”.
Changed the part ordering information accordingly.
Updated the -233 MHz timing specs to match modified timing specs
achieved by design (main affected params: t
f
Updated I/O standard Timing Delay Specs and changed the default I/O
standard from 3.3V PCI to LVCMOS.
Added paragraph about Delta39K being CompactPCI hot swap Ready.
Added X8 mode in the PLL description.
Added Standby ICC spec.
Updated the recommended boot PROM for 39K165/200 to be CY3LV002
instead of CY3LV020.
Updated Delta39K family offering.
Modified PLL timing parameters t
t
Deleted exception to CompactPCI Hot Swap compliance regarding “PCI
buffers....”
Added reference to app note “Hot Socketing Delta39K.”
Revised CompactPCI Hot Swap Specification R1.0 to be R2.0.
Combined with spec# 38-03040.
Updated pin-tables for 39K30 (208PQFP, 256FBGA) (p. 53-93)
Updated pin-tables for 39K50 (208PQFP, 256/484FBGA, 388BGA) (p.53-
93)
Added X3, X5, X6, X16 multiplication modes to Spread Aware PLL (p. 11)
Added PLL parameters (f
Added and updated Storage Temperature for 39K200-208EQFP (p.16)
Changed the I
Updated tCLZ, tCHMCYC2 parameter Values for -233MHz bin
Updated Input and Output Standard Timing Delay Adjustment table (p. 24)
Removed Self Boot Industrial parts from the offering
Removed Delta39K165Z (1.8V) from the offering
Removed 144 FBGA package offering
Added self-boot Flash Memory endurance and data retention data (p. 2)
Added Family, Package, and Density Migration section (p. 13)
Added note 20 to 484/676 FBGA pin table to identify slow 39K165 IOs (page
82)
MAX2
INDUTY
, t
CLMAA
parameter.
, t
cc0
CLMCYC2
spec for 39K165 and 39K200 (p.16)
, t
Description of Change
PLLVCO
CHMCYC2
, P
DWSA
, t
SAPLLI
CHMCLK
, t
DWOSA
, f
Delta39K™ ISR™
MPPLI
PD
).
, t
, t
)
MCCO
MCCJ
CPLD Family
, and t
, t
IOS
, t
LOCK
SCS
Page 91 of 91
, t
. Added
SCS2
,