CY39200V388-125MGC Cypress Semiconductor Corp, CY39200V388-125MGC Datasheet - Page 12

• Manufacturer Part Number: CY39200V388-125MGC
• Description: IC CPLD 200K GATE 388-BGA
• Manufacturer: Cypress Semiconductor Corp
• Series: Delta 39K™ ISR™r

Specifications of CY39200V388-125MGC

• Programmable Type: In-System Reprogrammable™ (ISR™) Flash
• Delay Time Tpd(1) Max: 10.0ns
• Voltage Supply - Internal: 2.5V, 3.3V
• Number Of Macrocells: 3072
• Number Of Gates: 288000
• Number Of I /o: 294
• Operating Temperature: 0°C ~ 70°C
• Mounting Type: Surface Mount
• Package / Case: 388-BGA
• Voltage: 1.8V, 2.5V, 3.3V
• Memory Type: FLASH
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Features: -
• Number Of Logic Elements/cells: -
• Other names: 428-1297

Table 2. Valid PLL Multiply and Divide Options—without External Feedback
tions. In general, PLLs are used to implement time-division-
multiplex circuits to achieve higher performance with fewer
device resources.
For example, a system that operates on a 32-bit data path that
runs at 40 MHz can be implemented with 16-bit circuitry that
runs internally at 80 MHz. PLLs can also be used to take
advantage of the positioning of the internally generated clock
edges to shift performance towards improved setup, hold or
clock-to-out times.
There are several frequency multiply (X1, X2, X3, X4, X5, X6,
X8, X16) and divide (/1, /2, /3, /4, /5, /6, /8, /16) options
available to create a wide range of clock frequencies from a
single clock input (GCLK[0]). For increased flexibility, there are
seven phase shifting options which allow clock skew/de-skew
by 45°, 90°, 135°, 180°, 225°, 270°, or 315°.
The Spread Aware feature refers to the ability of the PLL to
track a spread-spectrum input clock such that its spread is
seen on the output clock with the PLL staying locked. The total
amount of spread on the input clock should be limited to 0.6%
of the fundamental frequency. Spread Aware feature is
supported only with X1, X2, and X4 multiply options.
The Voltage Controlled Oscillator (VCO), the core of the
Delta39K PLL is designed to operate within the frequency
range of 100 MHz to 266 MHz. Hence, the multiply option
combined with input (GCLK[0]) frequency should be selected
such that this VCO operating frequency requirement is met.
This is demonstrated in Table 2 (columns 1, 2, and 3).
Table 3. Valid PLL Multiply and Divide Options — with External Feedback
Document #: 38-03039 Rev. *D
Input (GCLK) Frequency
Input Frequency
12.5-16.625
f
(GCLK[0])
16.67-44.33
PLLI
f
33.3-88.7
16.6-44.3
12.5-33.25
12.5-22.17
12.5-16.63
DC-12.5
100-133
12.5- 33
PLLI
20-53.2
12.5-26.6
50-133
25-66.5
25-66
50-133
(MHz)
(MHz)
Value
N/A
Valid Multiply Options
16
Value
1
2
3
4
5
6
8
1
1
1
1
1
1
1
Valid Multiply Options
PRELIMINARY
Frequency (MHz)
VCO Output
Frequency (MHz)
100-133
100-266
100-266
100-266
100-266
100-266
100-266
200-266
VCO Output
N/A
100-266
100-266
100-266
100-266
125-266
150-266
200-266
1 – 6, 8, 16
1 – 6, 8, 16
1 – 6, 8, 16
1 – 6, 8, 16
1 – 6, 8, 16
1 – 6, 8, 16
1 – 6, 8, 16
1 – 6, 8, 16
Value
N/A
Value
Another feature of this PLL is the ability to drive the output
clock (INTCLK) off the Delta39K chip to clock other devices on
the board, as shown in Figure 9 above. This off-chip clock is
half the frequency of the output clock as it has to go through a
register (I/O register or a macrocell register).
This PLL can also be used for board de-skewing purpose by
driving a PLL output clock off-chip, routing it to the other
devices on the board and feeding it back to the PLL’s external
feedback input (GCLK[1]). When this feature is used, only
limited multiply, divide and phase shift options can be used.
Table 2 describes the valid multiply and divide options that can
be used without external feedback. Table 3 describes the valid
multiply and divide options that can be used with an external
feedback.
Table 4 describes the valid phase shift options that can be
used with or without an external feedback.
Table 5 is an example of the effect of all the available divide
and phase shift options on a VCO output of 250 MHz. It also
shows the effect of division on the duty cycle of the resultant
clock. Note that the duty cycle is 50-50 when a VCO output is
divided by an even number. Also note that the phase shift
applies to the VCO output and not to the divided output.
The Spread Aware PLL operates as specified for Delta39KV
devices (2.5V/3.3V), but not Delta39KZ devices (1.8V). For
more details on the architecture and operation of this PLL
please refer to the application note entitled “Delta39K PLL and
Clock Tree”.
1
2
3
4
5
6
8
Output Frequency (INTCLK[3:0])
Output (INTCLK) Frequency
Valid Divide Options
f
33.33-88.66
f
Valid Divide Options
PLLO
PLLO
25 - 44.34
25 - 33.25
25 - 66.5
6.25-133
6.25-266
6.25-266
6.25-266
6.25-266
6.25-266
6.25-266
6.25-266
100-266
25 -53.2
DC-12.5
50-133
(MHz)
(MHz)
Delta39K™ ISR™
CPLD Family
Off-chip Clock
Off-chip Clock
16.67-44.33
Frequency
12.5-33.25
12.5-22.17
12.5-16.63
12.5-26.6
Frequency
Page 12 of 91
3.125-133
3.125-133
3.125-133
3.125-133
25-66.5
50-133
3.125-66
DC-6.25
3.1-266
3.1-133
3.1-133