CY39200V388-125MGC Cypress Semiconductor Corp, CY39200V388-125MGC Datasheet - Page 18

• Manufacturer Part Number: CY39200V388-125MGC
• Description: IC CPLD 200K GATE 388-BGA
• Manufacturer: Cypress Semiconductor Corp
• Series: Delta 39K™ ISR™r

Specifications of CY39200V388-125MGC

• Programmable Type: In-System Reprogrammable™ (ISR™) Flash
• Delay Time Tpd(1) Max: 10.0ns
• Voltage Supply - Internal: 2.5V, 3.3V
• Number Of Macrocells: 3072
• Number Of Gates: 288000
• Number Of I /o: 294
• Operating Temperature: 0°C ~ 70°C
• Mounting Type: Surface Mount
• Package / Case: 388-BGA
• Voltage: 1.8V, 2.5V, 3.3V
• Memory Type: FLASH
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Features: -
• Number Of Logic Elements/cells: -
• Other names: 428-1297

Power-up Sequence Requirements
Switching Characteristics — Parameter Descriptions
Document #: 38-03039 Rev. *D
Note:
12. Add t
• Upon power-up, all the outputs remain three-stated until all
• The part will not start configuration until V
t
t
t
t
t
t
Synchronous Clocking Parameters
t
t
t
t
t
t
t
t
t
t
t
t
f
f
PD
EA
ER
PRR
PRO
PRW
MCS
MCH
MCCO
IOS
IOH
IOCO
SCS
SCS2
ICS
OCS
CHZ
CLZ
MAX
MAX2
Combinatorial Mode Parameters
the V
the part has completed configuration.
V
nominal voltage.
CCJTAG
Parameter
CC
CHSW
pins have powered-up to the nominal voltage and
, V
to signals making a horizontal to vertical channel switch or vice-versa.
CCCNFG
Delay from any pin input, through any cluster on the channel associated with that pin input, to any pin
output on the horizontal or vertical channel associated with that cluster
Global control to output enable
Global control to output disable
Asynchronous macrocell RESET or PRESET recovery time from any pin input on the horizontal or vertical
channel associated with the cluster the macrocell is in
Asynchronous macrocell RESET or PRESET from any pin input on the horizontal or vertical channel
associated with the cluster that the macrocell is in to any pin output on those same channels
Asynchronous macrocell RESET or PRESET minimum pulse width, from any pin input to a macrocell in
the farthest cluster on the horizontal or vertical channel the pin is associated with
Set-up time of any input pin to a macrocell in any cluster on the channel associated with that input pin,
relative to a global clock
Hold time of any input pin to a macrocell in any cluster on the channel associated with that input pin, relative
to a global clock
Global clock to output of any macrocell to any output pin on the horizontal or vertical channel associated
with the cluster that macrocell is in
Set-up time of any input pin to the I/O cell register associated with that pin, relative to a global clock
Hold time of any input pin to the I/O cell register associated with that pin, relative to a global clock
Clock to output of an I/O cell register to the output pin associated with that register
Macrocell clock to macrocell clock through array logic within the same cluster
Macrocell clock to macrocell clock through array logic in different clusters on the same channel
I/O register clock to any macrocell clock in a cluster on the channel the I/O register is associated with
Macrocell clock to any I/O register clock on the horizontal or vertical channel associated with the cluster
that the macrocell is in
Clock to output disable (high-impedance)
Clock to output enable (low-impedance)
Maximum frequency with internal feedback—within the same cluster
Maximum frequency with internal feedback—within different clusters at the opposite ends of a horizontal
or vertical channel
, V
CCPLL
and V
PRELIMINARY
CCPRG
have reached
CC
, V
CCIO
,
• V
• All V
• All V
• Maximum ramp time for all V
Description
V
and powered up together.
to at least 1.5V before configuration has completed.
voltage in 100 ms.
Over the Operating Range
CC
CC
, V
CCIO
pins can be powered up in any order. This includes
CCIO
CCIO
s (even the unused banks) need to be powered up
s on a bank should be tied to the same potential
, V
CCJTAG
, V
CCCNFG
Delta39K™ ISR™
[12]
CC
s should be 0V to nominal
, V
CPLD Family
CCPLL
and V
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CCPRG
.