CY39200V388-125MGC Cypress Semiconductor Corp, CY39200V388-125MGC Datasheet - Page 8

• Manufacturer Part Number: CY39200V388-125MGC
• Description: IC CPLD 200K GATE 388-BGA
• Manufacturer: Cypress Semiconductor Corp
• Series: Delta 39K™ ISR™r

Specifications of CY39200V388-125MGC

• Programmable Type: In-System Reprogrammable™ (ISR™) Flash
• Delay Time Tpd(1) Max: 10.0ns
• Voltage Supply - Internal: 2.5V, 3.3V
• Number Of Macrocells: 3072
• Number Of Gates: 288000
• Number Of I /o: 294
• Operating Temperature: 0°C ~ 70°C
• Mounting Type: Surface Mount
• Package / Case: 388-BGA
• Voltage: 1.8V, 2.5V, 3.3V
• Memory Type: FLASH
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Features: -
• Number Of Logic Elements/cells: -
• Other names: 428-1297

.
The clocks for each port of the Dual-Port configuration are
selected from four global clocks and two local clocks. One
local clock is sourced from the horizontal channel and the
other from the vertical channel. The data outputs of the dual-
port memory can also be registered. Clocks for the output
registers are also selected from four global clocks and two
local clocks. One clock polarity mux per port allows the use of
true or complement polarity for input and output clocking
purposes.
Arbitration
The Dual-Port configuration of the Channel Memory Block
provides arbitration when both ports access the same address
at the same time. Depending on the memory operation being
attempted, one port always gets priority. See Table 1 for details
on which port gets priority for Read and Write operations. An
active-LOW “Address Match” signal is generated when an
address collision occurs.
Table 1. Arbitration Result: Address Match Signal
Becomes Active
Document #: 38-03039 Rev. *D
Port A Port B
Read
Write
Read
Read
Result of
Arbitration
No arbitration
required
Port A gets
priority
Cluster PIM
Both ports read at the
same time
If Port B requests first
then it will read the cur-
rent data. The output will
then change to the newly
written data by Port A
GCLK[3:0]
RESET
Figure 5. Block Diagram of Cluster Memory Block
PRELIMINARY
Local CLK
GCLK[3:0]
Local CLK
DOUT[7:0]
ADDR[12:0]
Comment
DIN[7:0]
WE
3
3
5:1
5:1
C
C
Q
D
D
D
R
C
D
Q
Q
Q
Table 1. Arbitration Result: Address Match Signal
Becomes Active
FIFO (Channel Memory) Configuration
The channel memory blocks are also configurable as
synchronous FIFO RAM. In the FIFO mode of operation, the
channel memory block supports all normal FIFO operations
without the use of any general-purpose logic resources in the
device.
The FIFO block contains all of the necessary FIFO flag logic,
including the Read and Write address pointers. The FIFO flags
include an empty/full flag (EF), half-full flag (HF), and program-
mable almost-empty/full (PAEF) flag output. The FIFO config-
uration has the ability to perform simultaneous Read and Write
operations using two separate clocks. These clocks may be
tied together for a single operation or may run independently
for asynchronous Read/Write (with regard to each other) appli-
cations. The data and control inputs to the FIFO block are
driven from the horizontal or vertical routing channels. The
data and flag outputs are driven onto dedicated routing tracks
in both the horizontal and vertical routing channels. This allows
the FIFO blocks to be expanded by using multiple FIFO blocks
Port A Port B
Read
Write
C
C
C
Control
2
Read
Logic
3
Write
Write
C
3
10
Result of
Arbitration
Port B gets
priority
Port A gets
priority
2
C
Asynchronous
Control
Logic
Write
Delta39K™ ISR™
1024x8
SRAM
8
8
If Port A requests first
then it will read the cur-
rent data. The output will
then change to the newly
written data by Port B
Port B is blocked until
Port A is finished writing
CPLD Family
Comment
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