CY39200V388-125MGC Cypress Semiconductor Corp, CY39200V388-125MGC Datasheet - Page 51

• Manufacturer Part Number: CY39200V388-125MGC
• Description: IC CPLD 200K GATE 388-BGA
• Manufacturer: Cypress Semiconductor Corp
• Series: Delta 39K™ ISR™r

Specifications of CY39200V388-125MGC

• Programmable Type: In-System Reprogrammable™ (ISR™) Flash
• Delay Time Tpd(1) Max: 10.0ns
• Voltage Supply - Internal: 2.5V, 3.3V
• Number Of Macrocells: 3072
• Number Of Gates: 288000
• Number Of I /o: 294
• Operating Temperature: 0°C ~ 70°C
• Mounting Type: Surface Mount
• Package / Case: 388-BGA
• Voltage: 1.8V, 2.5V, 3.3V
• Memory Type: FLASH
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Features: -
• Number Of Logic Elements/cells: -
• Other names: 428-1297

Pin Tables
Table 6. Pin Definition Table
Document #: 38-03039 Rev. *D
Notes:
18. The PLL is available in Delta39K ‘V’ devices (2.5V/3.3V) and not in Delta39K ‘Z’ devices (1.8V). In Delta39K ‘Z’ devices, connect V
Config_Done
Pin Name
V
GCLK0-3
GCTL0-3
IO/V
IO/V
IO/V
IO/V
IO/V
IO/V
IO/V
IO/V
IO6/Lock
V
Reconfig
V
V
CCPLL
V
V
V
V
V
V
V
V
MSEL
CCCNFG
CCLK
Reset
TCLK
CCJTAG
GND
CCPRG
TDO
TMS
CCE
Data
V
CCIO0
CCIO1
CCIO2
CCIO3
CCIO4
CCIO5
CCIO6
CCIO7
TDI
IO
CC
REF0
REF1
REF2
REF3
REF4
REF5
REF6
REF7
[18]
Function
Input
Input
Ground
Input/Output
Input/Output
Input/Output
Input/Output
Input/Output
Input/Output
Input/Output
Input/Output
Input/Output
Input/Output
Input
Input
Input
Input
Output
Input
Power
Power
Power
Power
Power
Power
Power
Power
Power
Power
Power
Power
Power
Output
Output
Output
Input
Output
Description
Global Clock signals 0 through 3
Global Control signals 0 through 3
Ground
Dual function pin: IO or Reference Voltage for Bank 0
Dual function pin: IO or Reference Voltage for Bank 1
Dual function pin: IO or Reference Voltage for Bank 2
Dual function pin: IO or Reference Voltage for Bank 3
Dual function pin: IO or Reference Voltage for Bank 4
Dual function pin: IO or Reference Voltage for Bank 5
Dual function pin: IO or Reference Voltage for Bank 6
Dual function pin: IO or Reference Voltage for Bank 7
Input or Output pin
Dual function pin: IO in Bank 6 or PLL lock output signal
Mode Select Pin (see Table 7)
Pin to start configuration of Delta39K
JTAG Test Clock
JTAG Test Data In
JTAG Test Data Out
JTAG Test Mode Select
Operating Voltage
V
V
V
V
V
V
V
V
V
V
V
V
Flag indicating that configuration is complete
Configuration Clock for serial interface with the external boot PROM
Chip select for the external boot PROM (active low)
Pin to receive configuration data from the external boot PROM
Reset signal to interface with the external boot PROM
PRELIMINARY
CC
CC
CC
CC
CC
CC
CC
CC
CC
CC
CC
CC
for I/O bank 0
for I/O bank 1
for I/O bank 2
for I/O bank 3
for I/O bank 4
for I/O bank 5
for I/O bank 6
for I/O bank 7
for JTAG pins
for Configuration port
for PLL
for programming the Self-Boot™ solution embedded boot PROM
Delta39K™ ISR™
CPLD Family
CCPLL
to V
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