CY39200V388-125MGC Cypress Semiconductor Corp, CY39200V388-125MGC Datasheet - Page 11

• Manufacturer Part Number: CY39200V388-125MGC
• Description: IC CPLD 200K GATE 388-BGA
• Manufacturer: Cypress Semiconductor Corp
• Series: Delta 39K™ ISR™r

Specifications of CY39200V388-125MGC

• Programmable Type: In-System Reprogrammable™ (ISR™) Flash
• Delay Time Tpd(1) Max: 10.0ns
• Voltage Supply - Internal: 2.5V, 3.3V
• Number Of Macrocells: 3072
• Number Of Gates: 288000
• Number Of I /o: 294
• Operating Temperature: 0°C ~ 70°C
• Mounting Type: Surface Mount
• Package / Case: 388-BGA
• Voltage: 1.8V, 2.5V, 3.3V
• Memory Type: FLASH
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Features: -
• Number Of Logic Elements/cells: -
• Other names: 428-1297

Slew Rate Control
The output buffer has a slew rate control option. This allows
the output buffer to slew at a fast rate (3 V/ns) or a slow rate
(1 V/ns). All I/Os default to fast slew rate. For designs
concerned with meeting FCC emissions standards the slow
edge provides for lower system noise. For designs requiring
very high performance the fast edge rate provides maximum
system performance.
Document #: 38-03039 Rev. *D
LVTTL
LVCMOS
LVCMOS3
LVCMOS2
LVCMOS18
3.3V PCI
GTL+
SSTL3 I
SSTL3 II
SSTL2 I
SSTL2 II
HSTL I
HSTL II
HSTL III
HSTL IV
Standard
I/O
Min.
1.15
1.15
0.68
0.68
0.68
0.68
0.9
1.3
1.3
GCLK0
V
REF
N/A
I/O Standards
GCLK1
2
fb
(V)
C
Source
Max.
X1, X2, X3, X4, 5X,
Clock
1.35
1.35
1.1
1.7
1.7
0.9
0.9
0.9
0.9
X6, X8, X16
INTCLK0, INTCLK1, INTCLK2, INTCLK3
PLL
Clock Tree
V
Clk 135
Clk 180
Delay
3.3V
3.3V
3.0V
2.5V
1.8V
3.3V
3.3V
3.3V
2.5V
2.5V
1.5V
1.5V
1.5V
1.5V
N/A
PRELIMINARY
Clk 45
off-chip signal (external feedback)
Figure 9. Block Diagram of Spread Aware PLL
CCIO
225
270
315
Clk
Clk
Clk
Clk
90
Lock
Clk
0
0
0
0
0
0
fb
0
0
0
Voltage (V
Termination
1.25
1.25
0.75
0.75
N/A
N/A
N/A
N/A
N/A
N/A
1.5
1.5
1.5
1.5
1.5
Phase selection
Phase selection
Phase selection
Phase selection
TT
Normal I/O signal path
)
Programmable Bus Hold
On each I/O pin, user-programmable-bus-hold is included.
Bus-hold, which is an improved version of the popular internal
pull-up resistor, is a weak latch connected to the pin that does
not degrade the device’s performance. As a latch, bus-hold
maintains the last state of a pin when the pin is placed in a
high-impedance state, thus reducing system noise in bus-
interface applications. Bus-hold additionally allows unused
device pins to remain unconnected on the board, which is
particularly useful during prototyping as designers can route
new signals to the device without cutting trace connections to
V
titled “Understanding Bus-Hold
CPLDs”.
Clocks
Delta39K has four dedicated clock input pins (GCLK[3:0]) to
accept system clocks. One of these clocks (GCLK[0]) may be
selected to drive an on-chip Phase-Locked Loop (PLL) for
frequency modulation (see Figure 9 for details).
The global clock tree for a Delta39K device can be driven by
a combination of the dedicated clock pins and/or the PLL-
derived clocks. The global clock tree consists of four global
clocks that go to every macrocell, memory block, and I/O cell.
Clock Tree Distribution
The global clock tree performs two primary functions. First, the
clock tree generates the four global clocks by multiplexing four
dedicated clocks from the package pins and four PLL driven
clocks. Second, the clock tree distributes the four global clocks
to every cluster, channel memory, and I/O block on the die.
The global clock tree is designed such that the clock skew is
minimized while maintaining an acceptable clock delay.
Spread Aware™ PLL
Each device in the Delta39K family features an on-chip PLL
designed using Spread Aware technology for low EMI applica-
CC
¸ 1-6,8,16
¸ 1-6,8,16
¸ 1-6,8,16
¸ 1-6,8,16
Any Register (TFF)
Divide
Divide
Divide
Divide
or GND. For more information, see the application note
C
Send a global clock off
GCLK2
Lock Detect/IO pin
GCLK0
GCLK1
GCLK3
chip
2
2
2
2
C
C
C
C
Delta39K™ ISR™
INTCLK1
INTCLK2
INTCLK3
INTCLK0
CPLD Family
A Feature of Cypress
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