DSPB56366AG120 Freescale Semiconductor, DSPB56366AG120 Datasheet - Page 16

• Manufacturer Part Number: DSPB56366AG120
• Description: IC DSP 24BIT AUD 120MHZ 144-LQFP
• Manufacturer: Freescale Semiconductor
• Series: Symphony™r
• Type: Audio Processorr

Specifications of DSPB56366AG120

• Interface: Host Interface, I²C, SAI, SPI
• Clock Rate: 120MHz
• Non-volatile Memory: ROM (240 kB)
• On-chip Ram: 69kB
• Voltage - I/o: 3.30V
• Voltage - Core: 3.30V
• Operating Temperature: -40°C ~ 110°C
• Mounting Type: Surface Mount
• Package / Case: 144-LQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

2.8
The SHI has five I/O signals that can be configured to allow the SHI to operate in either SPI or I
2-12
Signal
Name
MISO
MOSI
SCK
SCL
SDA
Serial Host Interface
Signal Type
open-drain
Input or
Input or
Input or
Input or
Input or
output
output
output
output
output
State during
Tri-stated
Tri-stated
Tri-stated
Tri-stated
Tri-stated
Reset
Table 2-10 Serial Host Interface Signals
SPI Serial Clock—The SCK signal is an output when the SPI is configured as a
master and a Schmitt-trigger input when the SPI is configured as a slave. When the
SPI is configured as a master, the SCK signal is derived from the internal SHI clock
generator. When the SPI is configured as a slave, the SCK signal is an input, and
the clock signal from the external master synchronizes the data transfer. The SCK
signal is ignored by the SPI if it is defined as a slave and the slave select (SS) signal
is not asserted. In both the master and slave SPI devices, data is shifted on one
edge of the SCK signal and is sampled on the opposite edge where data is stable.
Edge polarity is determined by the SPI transfer protocol.
I
SCL is a Schmitt-trigger input when configured as a slave and an open-drain output
when configured as a master. SCL should be connected to V
resistor.
This signal is tri-stated during hardware, software, and individual reset. Thus, there
is no need for an external pull-up in this state.
This input is 5 V tolerant.
SPI Master-In-Slave-Out—When the SPI is configured as a master, MISO is the
master data input line. The MISO signal is used in conjunction with the MOSI signal
for transmitting and receiving serial data. This signal is a Schmitt-trigger input when
configured for the SPI Master mode, an output when configured for the SPI Slave
mode, and tri-stated if configured for the SPI Slave mode when SS is deasserted.
An external pull-up resistor is not required for SPI operation.
I
receiving and an open-drain output when transmitting. SDA should be connected to
V
in SDA must be stable during the high period of SCL. The data in SDA is only
allowed to change when SCL is low. When the bus is free, SDA is high. The SDA
line is only allowed to change during the time SCL is high in the case of start and
stop events. A high-to-low transition of the SDA line while SCL is high is a unique
situation, and is defined as the start event. A low-to-high transition of SDA while
SCL is high is a unique situation defined as the stop event.
This signal is tri-stated during hardware, software, and individual reset. Thus, there
is no need for an external pull-up in this state.
This input is 5 V tolerant.
SPI Master-Out-Slave-In—When the SPI is configured as a master, MOSI is the
master data output line. The MOSI signal is used in conjunction with the MISO
signal for transmitting and receiving serial data. MOSI is the slave data input line
when the SPI is configured as a slave. This signal is a Schmitt-trigger input when
configured for the SPI Slave mode.
2
2
DSP56366 Technical Data, Rev. 3.1
CC
C Serial Clock—SCL carries the clock for I
C Data and Acknowledge—In I
through a pull-up resistor. SDA carries the data for I
Signal Description
2
C mode, SDA is a Schmitt-trigger input when
2
C bus transactions in the I
2
C transactions. The data
Freescale Semiconductor
CC
through a pull-up
2
2
C mode.
C mode.