DSPB56366AG120 Freescale Semiconductor, DSPB56366AG120 Datasheet - Page 19

• Manufacturer Part Number: DSPB56366AG120
• Description: IC DSP 24BIT AUD 120MHZ 144-LQFP
• Manufacturer: Freescale Semiconductor
• Series: Symphony™r
• Type: Audio Processorr

Specifications of DSPB56366AG120

• Interface: Host Interface, I²C, SAI, SPI
• Clock Rate: 120MHz
• Non-volatile Memory: ROM (240 kB)
• On-chip Ram: 69kB
• Voltage - I/o: 3.30V
• Voltage - Core: 3.30V
• Operating Temperature: -40°C ~ 110°C
• Mounting Type: Surface Mount
• Package / Case: 144-LQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Freescale Semiconductor
Signal
Name
SCKR
SDO5
SCKT
SDI0
PC4
PC0
PC3
FST
Input, output, or
Input, output, or
Input, output, or
Input or output
Input or output
Input or output
disconnected
disconnected
disconnected
Signal Type
Output
Input
Table 2-11 Enhanced Serial Audio Interface Signals (continued)
disconnected
disconnected
disconnected
disconnected
disconnected
disconnected
disconnected
State during
Reset
GPIO
GPIO
GPIO
GPIO
GPIO
GPIO
GPIO
DSP56366 Technical Data, Rev. 3.1
Frame Sync for Transmitter—This is the transmitter frame sync input/output
signal. For synchronous mode, this signal is the frame sync for both
transmitters and receivers. For asynchronous mode, FST is the frame sync for
the transmitters only. The direction is determined by the transmitter frame
sync direction (TFSD) bit in the ESAI transmit clock control register (TCCR).
Port C 4—When the ESAI is configured as GPIO, this signal is individually
programmable as input, output, or internally disconnected.
The default state after reset is GPIO disconnected.
This input is 5 V tolerant.
Receiver Serial Clock—SCKR provides the receiver serial bit clock for the
ESAI. The SCKR operates as a clock input or output used by all the enabled
receivers in the asynchronous mode (SYN=0), or as serial flag 0 pin in the
synchronous mode (SYN=1).
When this pin is configured as serial flag pin, its direction is determined by the
RCKD bit in the RCCR register. When configured as the output flag OF0, this
pin will reflect the value of the OF0 bit in the SAICR register, and the data in
the OF0 bit will show up at the pin synchronized to the frame sync in normal
mode or the slot in network mode. When configured as the input flag IF0, the
data value at the pin will be stored in the IF0 bit in the SAISR register,
synchronized by the frame sync in normal mode or the slot in network mode.
Port C 0—When the ESAI is configured as GPIO, this signal is individually
programmable as input, output, or internally disconnected.
The default state after reset is GPIO disconnected.
This input is 5 V tolerant.
Transmitter Serial Clock—This signal provides the serial bit rate clock for the
ESAI. SCKT is a clock input or output used by all enabled transmitters and
receivers in synchronous mode, or by all enabled transmitters in
asynchronous mode.
Port C 3—When the ESAI is configured as GPIO, this signal is individually
programmable as input, output, or internally disconnected.
The default state after reset is GPIO disconnected.
This input is 5 V tolerant.
Serial Data Output 5—When programmed as a transmitter, SDO5 is used to
transmit data from the TX5 serial transmit shift register.
Serial Data Input 0—When programmed as a receiver, SDI0 is used to
receive serial data into the RX0 serial receive shift register.
Signal Description
2-15