DSPB56366AG120 Freescale Semiconductor, DSPB56366AG120 Datasheet - Page 44

• Manufacturer Part Number: DSPB56366AG120
• Description: IC DSP 24BIT AUD 120MHZ 144-LQFP
• Manufacturer: Freescale Semiconductor
• Series: Symphony™r
• Type: Audio Processorr

Specifications of DSPB56366AG120

• Interface: Host Interface, I²C, SAI, SPI
• Clock Rate: 120MHz
• Non-volatile Memory: ROM (240 kB)
• On-chip Ram: 69kB
• Voltage - I/o: 3.30V
• Voltage - Core: 3.30V
• Operating Temperature: -40°C ~ 110°C
• Mounting Type: Surface Mount
• Package / Case: 144-LQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

1
2
3
4
5
6
3-18
131 Page mode cycle time for two consecutive
132 CAS assertion to data valid (read)
133 Column address valid to data valid (read)
134 CAS deassertion to data not valid (read hold
135 Last CAS assertion to RAS deassertion
136 Previous CAS deassertion to RAS deassertion
137 CAS assertion pulse width
No.
150
151
152
153
154
155
156
No.
The number of wait states for Page mode access is specified in the DCR.
The refresh period is specified in the DCR.
All the timings are calculated for the worst case. Some of the timings are better for specific cases (e.g., t
read-after-read or write-after-write sequences).
Reduced DSP clock speed allows use of Page Mode DRAM with one Wait state (See
BRW[1:0] (DRAM control register bits) defines the number of wait states that should be inserted in each DRAM out-of-page
access.
RD deassertion will always occur after CAS deassertion; therefore, the restricted timing is t
Table 3-9 DRAM Page Mode Timings, One Wait State (Low-Power Applications)
accesses of the same direction
Page mode cycle time for mixed (read and write)
accesses
time)
CAS assertion to data not valid (write)
WR assertion to CAS assertion
Last RD assertion to RAS deassertion
RD assertion to data valid
RD deassertion to data not valid
WR assertion to data active
WR deassertion to data high impedance
Characteristics
Characteristics
Table 3-10 DRAM Page Mode Timings, Two Wait States
6
DSP56366 Technical Data, Rev. 3.1
Symbol
t
t
WCS
t
ROH
t
t
DH
GA
Symbol
GZ
t
t
t
RHCP
t
t
t
RSH
CAC
t
OFF
CAS
PC
AA
0.75 × T
0.75 × T
1.5 × T
Expression
0.25 × T
1.75 × T
3.25 × T
T
T
1.5 × T
1.5 × T
2.5 × T
2.5 × T
1.5 × T
Expression
C
C
1.25 × T
− 4.3
− 7.5
2 × T
C
C
C
− 4.0
− 4.0
− 0.3
C
C
C
C
C
C
C
C
C
− 7.5
− 6.5
− 7.5
− 6.5
− 4.0
− 4.0
− 4.0
C
5
33.5
45.7
71.0
37.2
Min
0.0
—
—
20 MHz
45.4
41.1
22.5
45.2
18.7
Min
0.0
—
—
—
—
Figure 3-14
66 MHz
OFF
1, 2, 3, 4
Max
42.5
12.5
4
—
—
—
—
—
Max
15.2
30.4
—
—
—
—
—
—
—
—
and not t
1, 2, 3
Freescale Semiconductor
.).
21.0
29.0
46.0
24.7
Min
0.0
—
—
37.5
34.4
17.9
36.6
14.8
Min
0.0
30 MHz
—
—
—
—
PC
GZ
80 MHz
(continued)
.
equals 2 × T
25.8
Max
Max
12.3
24.8
8.3
4
—
—
—
—
—
—
—
—
—
—
—
—
—
Unit
Unit
ns
ns
ns
ns
ns
ns
ns
C
ns
ns
ns
ns
ns
ns
ns
ns
ns
for