DSPB56366AG120 Freescale Semiconductor, DSPB56366AG120 Datasheet - Page 47

• Manufacturer Part Number: DSPB56366AG120
• Description: IC DSP 24BIT AUD 120MHZ 144-LQFP
• Manufacturer: Freescale Semiconductor
• Series: Symphony™r
• Type: Audio Processorr

Specifications of DSPB56366AG120

• Interface: Host Interface, I²C, SAI, SPI
• Clock Rate: 120MHz
• Non-volatile Memory: ROM (240 kB)
• On-chip Ram: 69kB
• Voltage - I/o: 3.30V
• Voltage - Core: 3.30V
• Operating Temperature: -40°C ~ 110°C
• Mounting Type: Surface Mount
• Package / Case: 144-LQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

1
2
3
4
5
6
Freescale Semiconductor
No.
150 CAS assertion to data not valid (write)
151 WR assertion to CAS assertion
152 Last RD assertion to RAS deassertion
153 RD assertion to data valid
154 RD deassertion to data not valid
155 WR assertion to data active
156 WR deassertion to data high impedance
131
132
133
134
135
136
137
138
139
The number of wait states for Page mode access is specified in the DCR.
The refresh period is specified in the DCR.
The asynchronous delays specified in the expressions are valid for DSP56366.
All the timings are calculated for the worst case. Some of the timings are better for specific cases (e.g., t
read-after-read or write-after-write sequences).
BRW[1:0] (DRAM control register bits) defines the number of wait states that should be inserted in each DRAM out-of
page-access.
RD deassertion will always occur after CAS deassertion; therefore, the restricted timing is t
No.
Page mode cycle time for two consecutive accesses of the same
direction.
Page mode cycle time for mixed (read and write) accesses
CAS assertion to data valid (read)
Column address valid to data valid (read)
CAS deassertion to data not valid (read hold time)
Last CAS assertion to RAS deassertion
Previous CAS deassertion to RAS deassertion
CAS assertion pulse width
Last CAS deassertion to RAS assertion
CAS deassertion pulse width
• BRW[1:0] = 00
• BRW[1:0] = 01
• BRW[1:0] = 10
• BRW[1:0] = 11
Table 3-11 DRAM Page Mode Timings, Three Wait States
Table 3-12 DRAM Page Mode Timings, Four Wait States
Characteristics
Characteristics
6
DSP56366 Technical Data, Rev. 3.1
5
Symbol
t
t
t
RHCP
t
t
t
RSH
CRP
t
CAC
t
OFF
CAS
t
Symbol
PC
AA
CP
t
t
WCS
t
ROH
t
t
DH
GA
GZ
2.75 × T
3.75 × T
2.75 × T
4.25 × T
5.25 × T
7.25 × T
1, 2, 3
3.5 × T
2.5 × T
Expression
1.25 × T
0.75 × T
6 × T
2 × T
2.5 × T
3.5 × T
Expression
2.5 × T
4.5 × T
0.25 × T
5 × T
OFF
C
C
1, 2, 3
(continued)
C
C
C
C
C
C
C
C
− 4.0
− 4.0
C
C
C
C
− 4.0
− 4.0
C
C
and not t
− 7.0
− 7.0
− 6.0
− 6.0
− 6.0
− 6.0
C
− 4.0
− 4.0
− 7.0
− 4.3
− 0.3
C
4
4
41.7
37.5
25.2
46.0
16.8
37.7
54.4
12.7
21.0
31.0
Min
PC
Min
GZ
0.0
8.2
0.0
7.2
—
—
—
—
—
—
.
equals 4 × T
Max
15.9
24.2
Max
18.0
—
—
—
—
—
—
—
—
—
—
—
2.5
—
—
—
—
—
Unit
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
C
ns
ns
ns
ns
ns
ns
ns
3-21
for