DSPB56366AG120 Freescale Semiconductor, DSPB56366AG120 Datasheet - Page 34

• Manufacturer Part Number: DSPB56366AG120
• Description: IC DSP 24BIT AUD 120MHZ 144-LQFP
• Manufacturer: Freescale Semiconductor
• Series: Symphony™r
• Type: Audio Processorr

Specifications of DSPB56366AG120

• Interface: Host Interface, I²C, SAI, SPI
• Clock Rate: 120MHz
• Non-volatile Memory: ROM (240 kB)
• On-chip Ram: 69kB
• Voltage - I/o: 3.30V
• Voltage - Core: 3.30V
• Operating Temperature: -40°C ~ 110°C
• Mounting Type: Surface Mount
• Package / Case: 144-LQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

3-8
1
2
3
4
5
6
7
No.
27
28
29
V
Periodically sampled and not 100% tested.
RESET duration is measured during the time in which RESET is asserted, V
valid. When the V
the device circuitry will be in an uninitialized state that can result in significant power consumption and heat-up. Designs
should minimize this state to the shortest possible duration.
If PLL does not lose lock.
When using fast interrupts and IRQA, IRQB,
prevent multiple interrupt service. To avoid these timing restrictions, the deasserted Edge-triggered mode is recommended
when using fast interrupts. Long interrupts are recommended when using Level-sensitive mode.
WS = number of wait states (measured in clock cycles, number of T
This timing depends on several settings:
For PLL disable, using external clock (PCTL Bit 16 = 1), no stabilization delay is required and recovery time will be defined
by the PCTL Bit 17 and OMR Bit 6 settings.
For PLL enable, if PCTL Bit 17 is 0, the PLL is shutdown during Stop. Recovering from Stop requires the PLL to get locked.
The PLL lock procedure duration, PLL Lock Cycles (PLC), may be in the range of 0 to 1000 cycles. This procedure occurs in
parallel with the stop delay counter, and stop recovery will end when the last of these two events occurs: the stop delay
counter completes count or PLL lock procedure completion.
PLC value for PLL disable is 0.
The maximum value for ET
MHz = 34.1 μs). During the stabilization period, T
vary as well.
CC
Interrupt Requests Rate
DMA Requests Rate
Delay from IRQA, IRQB, IRQC, IRQD, NMI assertion to
external memory (DMA source) access address out valid
= 3.3 V ± 0.16 V; T
• HDI08, ESAI, ESAI_1, SHI, DAX, Timer
• DMA
• IRQ, NMI (edge trigger)
• IRQ (level trigger)
• Data read from HDI08, ESAI, ESAI_1, SHI, DAX
• Data write to HDI08, ESAI, ESAI_1, SHI, DAX
• Timer
• IRQ, NMI (edge trigger)
CC
Table 3-7 Reset, Stop, Mode Select, and Interrupt Timing
is valid, but the other “required RESET duration” conditions (as specified above) have not been yet met,
J
= –40°C to + 110°C, C
Characteristics
C
is 4096 (maximum MF) divided by the desired internal frequency (i.e., for 120 MHz it is 4096/120
DSP56366 Technical Data, Rev. 3.1
IRQC,
L
C
= 50 pF
, T
and IRQD are defined as level-sensitive, timings 19 through 21 apply to
H
, and T
L
will not be constant, and their width may vary, so timing may
C
). Use expression to compute maximum value.
4.25 × T
Expression
CC
12T
12T
is valid, and the EXTAL input is active and
8T
8T
6T
7T
2T
3T
C
C
C
C
C
C
C
C
C
+ 2.0
1
(continued)
Freescale Semiconductor
37.4
Min
—
—
—
—
—
—
—
100.0
100.0
Max
66.7
66.7
50.0
58.0
16.7
25.0
—
Unit
ns
ns
ns
ns
ns
ns
ns
ns