DSPB56366AG120 Freescale Semiconductor, DSPB56366AG120 Datasheet - Page 32

• Manufacturer Part Number: DSPB56366AG120
• Description: IC DSP 24BIT AUD 120MHZ 144-LQFP
• Manufacturer: Freescale Semiconductor
• Series: Symphony™r
• Type: Audio Processorr

Specifications of DSPB56366AG120

• Interface: Host Interface, I²C, SAI, SPI
• Clock Rate: 120MHz
• Non-volatile Memory: ROM (240 kB)
• On-chip Ram: 69kB
• Voltage - I/o: 3.30V
• Voltage - Core: 3.30V
• Operating Temperature: -40°C ~ 110°C
• Mounting Type: Surface Mount
• Package / Case: 144-LQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

3.8
3.9
3-6
1
2
3
4
No.
10
13
8
9
Measured at 50% of the input transition.
The maximum value for PLL enabled is given for minimum V
The indicated duty cycle is for the specified maximum frequency for which a part is rated. The minimum clock high or low time
required for correct operation, however, remains the same at lower operating frequencies; therefore, when a lower clock
frequency is used, the signal symmetry may vary from the specified duty cycle as long as the minimum high time and low time
requirements are met.
The maximum value for PLL enabled is given for minimum VCO and maximum DF.
No.
1
V
PLL external capacitor (PCAP pin to V
4
7
• @ MF ≤ 4
• @ MF > 4
CO
C
for C
(MF x 680)-120
PCAP
Delay from RESET assertion to all pins at reset value
Required RESET duration
Delay from asynchronous RESET deassertion to first
external address output (internal reset deassertion)
Mode select setup time
• Power on, external clock generator, PLL disabled
• Power on, external clock generator, PLL enabled
• During normal operation
• Minimum
• Maximum
frequency when PLL enabled (MF × E
EXTAL cycle time
Instruction cycle time = I
PCAP
• With PLL disabled
• With PLL enabled
• With PLL disabled
• With PLL enabled
Phase Lock Loop (PLL) Characteristics
Reset, Stop, Mode Select, and Interrupt Timing
is the value of the PLL capacitor (connected between the PCAP pin and V
can be computed from one of the following equations:
, for MF ≤ 4 or
Characteristics
2
Table 3-7 Reset, Stop, Mode Select, and Interrupt Timing
Characteristics
3
CYC
MF x 1100
= T
Characteristics
Table 3-5 Clock Operation (continued)
CCP
C
4, 2
DSP56366 Technical Data, Rev. 3.1
Table 3-6 PLL Characteristics
) (C
f
× 2/PDF)
, for MF > 4.
PCAP
)
1
4
2
CO
and maximum MF.
(MF × 580) − 100
MF × 830
Min
30
20.25 T
3.25 × T
Expression
1000 × ET
50 × ET
2.5 × T
—
C
C
CCP
+ 7.50
+ 2.0
C
C
Symbol
C
I
ET
). The recommended value in pF
CYC
(MF × 780) − 140
C
MF × 1470
1
Max
240
Freescale Semiconductor
16.66 ns
8.33 ns
8.33 ns
8.33 ns
416.7
20.8
29.1
30.0
Min
Min
8.3
—
—
176.2
Max
26.0
—
—
—
—
—
273.1 μs
MHz
Unit
8.53 μs
pF
Max
∞
∞
Unit
ns
ns
μs
ns
ns
ns
ns