EP1K10TC100-3 Altera, EP1K10TC100-3 Datasheet - Page 28

IC ACEX 1K FPGA 10K 100-TQFP

EP1K10TC100-3

Manufacturer Part Number
EP1K10TC100-3
Description
IC ACEX 1K FPGA 10K 100-TQFP
Manufacturer
Altera
Series
ACEX-1K®r
Datasheet

Specifications of EP1K10TC100-3

Number Of Logic Elements/cells
576
Number Of Labs/clbs
72
Total Ram Bits
12288
Number Of I /o
66
Number Of Gates
56000
Voltage - Supply
2.375 V ~ 2.625 V
Mounting Type
Surface Mount
Operating Temperature
0°C ~ 70°C
Package / Case
100-TQFP, 100-VQFP
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Other names
544-1027

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
EP1K10TC100-3
Manufacturer:
Altera
Quantity:
10 000
Part Number:
EP1K10TC100-3
Manufacturer:
ALTERA
0
Company:
Part Number:
EP1K10TC100-3
Manufacturer:
ALTERA
Quantity:
106
Part Number:
EP1K10TC100-3
Manufacturer:
ALTERA
Quantity:
200
Part Number:
EP1K10TC100-3N
Manufacturer:
Altera
Quantity:
10 000
Part Number:
EP1K10TC100-3N
Manufacturer:
ALTERA
0
Part Number:
EP1K10TC100-3N
Manufacturer:
ALTERA
Quantity:
1 000
Part Number:
EP1K10TC100-3N
Manufacturer:
ALTERA
Quantity:
1 000
Part Number:
EP1K10TC100-3N
Manufacturer:
ALTERA
Quantity:
1 000
ACEX 1K Programmable Logic Device Family Data Sheet
28
For improved routing, the row interconnect consists of a combination of
full-length and half-length channels. The full-length channels connect to
all LABs in a row; the half-length channels connect to the LABs in half of
the row. The EAB can be driven by the half-length channels in the left half
of the row and by the full-length channels. The EAB drives out to the full-
length channels. In addition to providing a predictable, row-wide
interconnect, this architecture provides increased routing resources. Two
neighboring LABs can be connected using a half-row channel, thereby
saving the other half of the channel for the other half of the row.
Table 6
resources available in each ACEX 1K device.
In addition to general-purpose I/O pins, ACEX 1K devices have six
dedicated input pins that provide low-skew signal distribution across the
device. These six inputs can be used for global clock, clear, preset, and
peripheral output-enable and clock-enable control signals. These signals
are available as control signals for all LABs and IOEs in the device. The
dedicated inputs can also be used as general-purpose data inputs because
they can feed the local interconnect of each LAB in the device.
Figure 14
row, column, and local interconnects, as well as the associated cascade
and carry chains. Each LAB is labeled according to its location: a letter
represents the row and a number represents the column. For example,
LAB B3 is in row B, column 3.
EP1K10
EP1K30
EP1K50
EP1K100
Table 6. ACEX 1K FastTrack Interconnect Resources
Device
summarizes the FastTrack Interconnect routing structure
shows the interconnection of adjacent LABs and EABs, with
Rows
10
12
3
6
Channels per
Row
144
216
216
312
Columns
24
36
36
52
Altera Corporation
Channels per
Column
24
24
24
24

Related parts for EP1K10TC100-3