EP1K10TC100-3 Altera, EP1K10TC100-3 Datasheet - Page 33

IC ACEX 1K FPGA 10K 100-TQFP

EP1K10TC100-3

Manufacturer Part Number
EP1K10TC100-3
Description
IC ACEX 1K FPGA 10K 100-TQFP
Manufacturer
Altera
Series
ACEX-1K®r
Datasheet

Specifications of EP1K10TC100-3

Number Of Logic Elements/cells
576
Number Of Labs/clbs
72
Total Ram Bits
12288
Number Of I /o
66
Number Of Gates
56000
Voltage - Supply
2.375 V ~ 2.625 V
Mounting Type
Surface Mount
Operating Temperature
0°C ~ 70°C
Package / Case
100-TQFP, 100-VQFP
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Other names
544-1027
Altera Corporation
Figure 16. ACEX 1K Row-to-IOE Connections
Note:
(1)
The values for m and n are shown in
Row FastTrack
Interconnect
n
Row-to-IOE Connections
When an IOE is used as an input signal, it can drive two separate row
channels. The signal is accessible by all LEs within that row. When an IOE
is used as an output, the signal is driven by a multiplexer that selects a
signal from the row channels. Up to eight IOEs connect to each side of
each row channel (see
Table 8
EP1K10
EP1K30
EP1K50
EP1K100
Table 8. ACEX 1K Row-to-IOE Interconnect Resources
Device
lists the ACEX 1K row-to-IOE interconnect resources.
Table
Each IOE can drive two
row channels.
n
n
m
m
8.
Note (1)
ACEX 1K Programmable Logic Device Family Data Sheet
Figure
Channels per Row (n)
m-to-1 multiplexer.
Each IOE is driven by an
16).
144
216
216
312
IOE8
IOE1
Row Channels per Pin (m)
18
27
27
39
33
13

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