EP1K10QC208-3 Altera, EP1K10QC208-3 Datasheet - Page 51

• Manufacturer Part Number: EP1K10QC208-3
• Description: IC ACEX 1K FPGA 10K 208-PQFP
• Manufacturer: Altera
• Series: ACEX-1K®r

Specifications of EP1K10QC208-3

• Number Of Logic Elements/cells: 576
• Number Of Labs/clbs: 72
• Total Ram Bits: 12288
• Number Of I /o: 120
• Number Of Gates: 56000
• Voltage - Supply: 2.375 V ~ 2.625 V
• Mounting Type: Surface Mount
• Operating Temperature: 0°C ~ 70°C
• Package / Case: 208-MQFP, 208-PQFP
• No. Of I/o's: 120
• Operating Temperature Range: 0°C To +70°C
• Logic Case Style: QFP
• No. Of Pins: 208
• Peak Reflow Compatible (260 C): No
• No. Of Macrocells: 576
• Rohs Compliant: No
• Clock Management: PLL
• Leaded Process Compatible: No
• No. Of Gates: 10000
• No. Of Logic Blocks: 72
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Other names: 544-1090

Altera Corporation
Figure 24. ACEX 1K Device Timing Model
Figure 25. ACEX 1K Device LE Timing Model
Clock/Input
Dedicated
Control-In
Data-In
Carry-In
Figure 24
to and from the various elements of the ACEX 1K device.
Figures 25
and functions within the LE, IOE, EAB, and bidirectional timing models.
Packed Register
Register Control
Carry Chain
t
t
t
t
t
t
t
t
t
LUT Delay
PACKED
LUT
RLUT
CLUT
C
EN
CGEN
CGENR
CICO
shows the overall timing model, which maps the possible paths
Delay
Delay
Delay
through
t
Element
Cascade-In
LABCARRY
Carry-Out
Logic
ACEX 1K Programmable Logic Device Family Data Sheet
28
show the delays that correspond to various paths
Interconnect
Cascade-Out
t
LABCASC
t
CASC
Embedded Array
Block
Register
Delays
t
t
t
t
t
t
COMB
H
PRE
CLR
CO
SU
Data-Out
I/O Element
51
13