EP4CE115F29I8LN Altera, EP4CE115F29I8LN Datasheet - Page 241
![IC CYCLONE IV FPGA 115K 780-FBGA](/photos/6/72/67270/544-780-fbga_sml.jpg)
EP4CE115F29I8LN
Manufacturer Part Number
EP4CE115F29I8LN
Description
IC CYCLONE IV FPGA 115K 780-FBGA
Manufacturer
Altera
Series
CYCLONE® IV Er
Datasheets
1.EP4CGX15BN11C8N.pdf
(44 pages)
2.EP4CGX15BN11C8N.pdf
(14 pages)
3.EP4CGX15BN11C8N.pdf
(478 pages)
4.EP4CGX15BN11C8N.pdf
(10 pages)
Specifications of EP4CE115F29I8LN
Number Of Logic Elements/cells
114480
Number Of Labs/clbs
7155
Total Ram Bits
3888000
Number Of I /o
528
Voltage - Supply
0.97 V ~ 1.03 V
Mounting Type
Surface Mount
Operating Temperature
-40°C ~ 100°C
Package / Case
780-FBGA
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Number Of Gates
-
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Chapter 8: Configuration and Remote System Upgrades in Cyclone IV Devices
Remote System Upgrade
Table 8–21. Remote System Upgrade Control Register Contents
© December 2010 Altera Corporation
Wd_timer[11..0]
Ru_address[21..0] 22'b0000000000000000000000
Rsv1
Wd_en
Osc_int
Cd_early
Rsv2
Note to
(1) Option bit for the application configuration.
Control Register Bit
Table
(1)
8–21:
(1)
1
Figure 8–34. Remote System Upgrade Control Register
When enabled, the early CONF_DONE check (Cd_early) option bit ensures that there
is a valid configuration at the boot address specified by the factory configuration and
that it is of the proper size. If an invalid configuration is detected or the CONF_DONE
pin is asserted too early, the device resets and then reconfigures the factory
configuration image. The internal oscillator (as the startup state machine clock
[Osc_int] option bit) ensures a functional startup clock to eliminate the hanging of
startup. When all option bits are turned on, they provide complete coverage for the
programming and startup portions of the application configuration. Altera
recommends turning on both the Cd_early and Osc_int option bits.
The Cd_early and Osc_int option bits for the application configuration must be
turned on by the factory configuration.
Remote System Upgrade Status Register
The remote system upgrade status register specifies the reconfiguration trigger
condition. The various trigger and error conditions include:
■
■
■
■
■
Cyclical redundancy check (CRC) error during application configuration
nSTATUS assertion by an external device due to an error
Cyclone IV device logic array triggers a reconfiguration cycle, possibly after
downloading a new application configuration image
External configuration reset (nCONFIG) assertion
User watchdog timer time out
12'b000000000000
1'b0
1'b1
1'b1
1'b1
1'b1
Rsv2
38
Cd_early Osc_int Wd_en Rsv1 Ru_address[21..0] Wd_timer[11..0]
Value
37
36
35
User watchdog time-out value (most significant 12 bits of
29-bit count value:
{Wd_timer[11..0],17'b1000})
Configuration address (most significant 22 bits of 24-bit
boot address value:
boot_address[23:0] =
{Ru_address[21..0],2'b0})
Reserved bit
User watchdog timer enable bit
Internal oscillator as startup state machine clock enable bit
Early CONF_DONE check
Reserved bit
34 33
Definition
Cyclone IV Device Handbook, Volume 1
12 11
0
8–75
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