EP4CE115F29I8LN Altera, EP4CE115F29I8LN Datasheet - Page 403
![IC CYCLONE IV FPGA 115K 780-FBGA](/photos/6/72/67270/544-780-fbga_sml.jpg)
EP4CE115F29I8LN
Manufacturer Part Number
EP4CE115F29I8LN
Description
IC CYCLONE IV FPGA 115K 780-FBGA
Manufacturer
Altera
Series
CYCLONE® IV Er
Datasheets
1.EP4CGX15BN11C8N.pdf
(44 pages)
2.EP4CGX15BN11C8N.pdf
(14 pages)
3.EP4CGX15BN11C8N.pdf
(478 pages)
4.EP4CGX15BN11C8N.pdf
(10 pages)
Specifications of EP4CE115F29I8LN
Number Of Logic Elements/cells
114480
Number Of Labs/clbs
7155
Total Ram Bits
3888000
Number Of I /o
528
Voltage - Supply
0.97 V ~ 1.03 V
Mounting Type
Surface Mount
Operating Temperature
-40°C ~ 100°C
Package / Case
780-FBGA
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Number Of Gates
-
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Chapter 3: Cyclone IV Dynamic Reconfiguration
Dynamic Reconfiguration Modes
Figure 3–4. Write Transaction Waveform—Use ‘logical_channel_address port’ Option
Notes to
(1) In this waveform example, you are writing to only the transmitter portion of the channel.
(2) In this waveform example, the number of channels connected to the dynamic reconfiguration controller is four. Therefore, the
© December 2010 Altera Corporation
logical_channel_address port is 2 bits wide.
logical_channel_address [1:0]
Figure
rx_tx_duplex_sel [1:0]
3–4:
tx_vodctrl [2:0]
Figure 3–4
Read Transaction
For example, to read the existing V
the transmitter portion of a specific channel controlled by the ALTGX_RECONFIG
instance, perform the following steps:
1. Set the logical_channel_address input port to the logical channel address of the
2. Set the rx_tx_duplex_sel port to 2'b10 so that only the transmit PMA controls are
3. Ensure that the busy signal is low before you start a read transaction.
4. Assert the read signal for one reconfig_clk clock cycle. This initiates the read
The busy output status signal is asserted high to indicate that the dynamic
reconfiguration controller is busy reading the PMA control values. When the read
transaction has completed, the busy signal goes low. The data_valid signal is asserted
to indicate that the data available at the read control signal is valid.
reconfig_clk
transceiver channel whose PMA controls you want to read (for example,
tx_vodctrl_out).
read from the transceiver channel.
transaction.
write_all
busy
(2)
(1)
shows the write transaction waveform for Method 1.
3'b111
2'b00
2'b00
OD
values from the transmit V
3'b001
2'b10
2'b01
Cyclone IV Device Handbook, Volume 2
OD
control registers of
3–13
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