EP4CE115F29I8LN Altera, EP4CE115F29I8LN Datasheet - Page 30
![IC CYCLONE IV FPGA 115K 780-FBGA](/photos/6/72/67270/544-780-fbga_sml.jpg)
EP4CE115F29I8LN
Manufacturer Part Number
EP4CE115F29I8LN
Description
IC CYCLONE IV FPGA 115K 780-FBGA
Manufacturer
Altera
Series
CYCLONE® IV Er
Datasheets
1.EP4CGX15BN11C8N.pdf
(44 pages)
2.EP4CGX15BN11C8N.pdf
(14 pages)
3.EP4CGX15BN11C8N.pdf
(478 pages)
4.EP4CGX15BN11C8N.pdf
(10 pages)
Specifications of EP4CE115F29I8LN
Number Of Logic Elements/cells
114480
Number Of Labs/clbs
7155
Total Ram Bits
3888000
Number Of I /o
528
Voltage - Supply
0.97 V ~ 1.03 V
Mounting Type
Surface Mount
Operating Temperature
-40°C ~ 100°C
Package / Case
780-FBGA
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Number Of Gates
-
Available stocks
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Part Number
Manufacturer
Quantity
Price
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2–2
Figure 2–1. Cyclone IV Device LEs
LE Features
Cyclone IV Device Handbook, Volume 1
data 1
data 2
data 3
data 4
Figure 2–1
You can configure the programmable register of each LE for D, T, JK, or SR flipflop
operation. Each register has data, clock, clock enable, and clear inputs. Signals that
use the global clock network, general-purpose I/O pins, or any internal logic can
drive the clock and clear control signals of the register. Either general-purpose I/O
pins or the internal logic can drive the clock enable. For combinational functions, the
LUT output bypasses the register and drives directly to the LE outputs.
Each LE has three outputs that drive the local, row, and column routing resources.
The LUT or register output independently drives these three outputs. Two LE outputs
drive the column or row and direct link routing connections, while one LE drives the
local interconnect resources. This allows the LUT to drive one output while the
register drives another output. This feature, called register packing, improves device
utilization because the device can use the register and the LUT for unrelated
functions. The LAB-wide synchronous load control signal is not available when using
register packing. For more information about the synchronous load control signal,
refer to
The register feedback mode allows the register output to feed back into the LUT of the
same LE to ensure that the register is packed with its own fan-out LUT, providing
another mechanism for improved fitting. The LE can also drive out registered and
unregistered versions of the LUT output.
Register Feedback
LE Carry-In
Look-Up Table
“LAB Control Signals” on page
(LUT)
shows the LEs for Cyclone IV devices.
LE Carry-Out
Register Chain
Chain
Routing from
Carry
previous LE
(DEV_CLRn)
Chip-Wide
labclkena1
labclkena2
labclr1
labclr2
Reset
labclk2
labclk1
Synchronous
LAB-Wide
Chapter 2: Logic Elements and Logic Array Blocks in Cyclone IV Devices
Load
Asynchronous
Synchronous
Clock Enable
Clear Logic
Clear Logic
Load and
Clock &
Select
Synchronous
LAB-Wide
2–6.
Clear
Register Bypass
D
ENA
CLRN
Q
© November 2009 Altera Corporation
Register Chain
Output
Row, Column,
And Direct Link
Routing
Row, Column,
And Direct Link
Routing
Local
Routing
Logic Elements
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