EP4CE115F29I8LN Altera, EP4CE115F29I8LN Datasheet - Page 87
![IC CYCLONE IV FPGA 115K 780-FBGA](/photos/6/72/67270/544-780-fbga_sml.jpg)
EP4CE115F29I8LN
Manufacturer Part Number
EP4CE115F29I8LN
Description
IC CYCLONE IV FPGA 115K 780-FBGA
Manufacturer
Altera
Series
CYCLONE® IV Er
Datasheets
1.EP4CGX15BN11C8N.pdf
(44 pages)
2.EP4CGX15BN11C8N.pdf
(14 pages)
3.EP4CGX15BN11C8N.pdf
(478 pages)
4.EP4CGX15BN11C8N.pdf
(10 pages)
Specifications of EP4CE115F29I8LN
Number Of Logic Elements/cells
114480
Number Of Labs/clbs
7155
Total Ram Bits
3888000
Number Of I /o
528
Voltage - Supply
0.97 V ~ 1.03 V
Mounting Type
Surface Mount
Operating Temperature
-40°C ~ 100°C
Package / Case
780-FBGA
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Number Of Gates
-
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Chapter 5: Clock Networks and PLLs in Cyclone IV Devices
Clock Feedback Modes
Zero Delay Buffer Mode
Deterministic Latency Compensation Mode
© December 2010 Altera Corporation
In zero delay buffer (ZDB) mode, the external clock output pin is phase-aligned with
the clock input pin for zero delay through the device. When using this mode, use the
same I/O standard on the input clock and output clocks to guarantee clock alignment
at the input and output pins.
Figure 5–15
in ZDB mode.
Figure 5–15. Phase Relationship Between PLL Clocks in ZDB Mode
The deterministic latency mode compensates for the delay of the multipurpose PLLs
through the clock network and serializer in Common Public Radio Interface (CPRI)
applications. In this mode, the PLL PFD feedback path compensates the latency
uncertainty in Tx dataout and Tx clkout paths relative to the reference clock.
External PLL Clock Output
shows an example waveform of the phase relationship of the PLL clocks
at the Register Clock Port
PLL Reference Clock
at the Output Pin
at the Input Pin
PLL Clock
Phase Aligned
Cyclone IV Device Handbook, Volume 1
5–25
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