EP4CE115F29I8LN Altera, EP4CE115F29I8LN Datasheet - Page 52
![IC CYCLONE IV FPGA 115K 780-FBGA](/photos/6/72/67270/544-780-fbga_sml.jpg)
EP4CE115F29I8LN
Manufacturer Part Number
EP4CE115F29I8LN
Description
IC CYCLONE IV FPGA 115K 780-FBGA
Manufacturer
Altera
Series
CYCLONE® IV Er
Datasheets
1.EP4CGX15BN11C8N.pdf
(44 pages)
2.EP4CGX15BN11C8N.pdf
(14 pages)
3.EP4CGX15BN11C8N.pdf
(478 pages)
4.EP4CGX15BN11C8N.pdf
(10 pages)
Specifications of EP4CE115F29I8LN
Number Of Logic Elements/cells
114480
Number Of Labs/clbs
7155
Total Ram Bits
3888000
Number Of I /o
528
Voltage - Supply
0.97 V ~ 1.03 V
Mounting Type
Surface Mount
Operating Temperature
-40°C ~ 100°C
Package / Case
780-FBGA
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Number Of Gates
-
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3–16
Cyclone IV Device Handbook, Volume 1
Same-Port Read-During-Write Mode
This mode applies to a single-port RAM or the same port of a true dual-port RAM. In
the same port read-during-write mode, there are two output choices: New Data mode
(or flow-through) and Old Data mode. In New Data mode, new data is available on
the rising edge of the same clock cycle on which it was written. In Old Data mode, the
RAM outputs reflect the old data at that address before the write operation proceeds.
When using New Data mode together with byteena, you can control the output of
the RAM. When byteena is high, the data written into the memory passes to the
output (flow-through). When byteena is low, the masked-off data is not written into
the memory and the old data in the memory appears on the outputs. Therefore, the
output can be a combination of new and old data determined by byteena.
Figure 3–14
read-during-write behavior with both New Data and Old Data modes, respectively.
Figure 3–14. Same Port Read-During Write: New Data Mode
Figure 3–15. Same Port Read-During-Write: Old Data Mode
q_a (asynch)
q_a (asynch)
address_a
address_a
wren_a
wren_a
data_a
rden_a
rden_a
data_a
clk_a
clk_a
and
Figure 3–15
A
A
a0(old data)
show sample functional waveforms of same port
A
a0
B
a0
B
A
B
C
C
B
C
Chapter 3: Memory Blocks in Cyclone IV Devices
D
D
a1(old data)
D
© November 2009 Altera Corporation
a1
a1
E
E
D
E
Design Considerations
F
F
E
F
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