EP4CE115F29I8LN Altera, EP4CE115F29I8LN Datasheet - Page 388

• Manufacturer Part Number: EP4CE115F29I8LN
• Description: IC CYCLONE IV FPGA 115K 780-FBGA
• Manufacturer: Altera
• Series: CYCLONE® IV Er

Specifications of EP4CE115F29I8LN

• Number Of Logic Elements/cells: 114480
• Number Of Labs/clbs: 7155
• Total Ram Bits: 3888000
• Number Of I /o: 528
• Voltage - Supply: 0.97 V ~ 1.03 V
• Mounting Type: Surface Mount
• Operating Temperature: -40°C ~ 100°C
• Package / Case: 780-FBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of Gates: -

2–22
Simulation Requirements
Reference Information
Cyclone IV Device Handbook, Volume 2
The following are simulation requirements:
■
■
■
■
■
For more information about some useful reference terms used in this chapter, refer to
the links listed in
Table 2–7. Reference Information
Dynamic Reconfiguration Reset Sequences
The gxb_powerdown port is optional. In simulation, if the gxb_powerdown port
is not instantiated, you must assert the tx_digitalreset, rx_digitalreset,
and rx_analogreset signals appropriately for correct simulation behavior.
If the gxb_powerdown port is instantiated, and the other reset signals are not
used, you must assert the gxb_powerdown signal for at least 1 s for correct
simulation behavior.
You can deassert the rx_digitalreset signal immediately after the
rx_freqlocked signal goes high to reduce the simulation run time. It is not
necessary to wait for t
The busy signal is deasserted after about 20 parallel reconfig_clk clock cycles
in order to reduce simulation run time. For silicon behavior in hardware, you can
follow the reset sequences described in the previous pages.
In PCIe mode simulation, you must assert the tx_forceelecidle signal for at
least one parallel clock cycle before transmitting normal data for correct
simulation behavior.
Non-Bonded channel configuration
Bonded channel configuration
Terms Used in this Chapter
rx_digitalreset
tx_digitalreset
Automatic Lock Mode
rx_analogreset
gxb_powerdown
rx_freqlocked
Manual Lock Mode
pll_locked
pll_areset
Table
busy
PCIe
LTD
LTR
2–7.
LTD_Auto
(as suggested in the actual reset sequence).
Chapter 2: Cyclone IV Reset Control and Power Down
Useful Reference Points
© December 2010 Altera Corporation
page 2–18
page 2–10
page 2–16
page 2–7
page 2–6
page 2–3
page 2–2
page 2–6
page 2–6
page 2–9
page 2–2
page 2–2
page 2–2
page 2–2
page 2–3
page 2–2
Simulation Requirements