EP2AGX190FF35C6N Altera, EP2AGX190FF35C6N Datasheet - Page 101
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EP2AGX190FF35C6N
Manufacturer Part Number
EP2AGX190FF35C6N
Description
IC ARRIA II GX 190K 1152FBGA
Manufacturer
Altera
Series
Arria II GXr
Datasheets
1.EP2AGX45CU17C6N.pdf
(96 pages)
2.EP2AGX45CU17C6N.pdf
(14 pages)
3.EP2AGX45CU17C6N.pdf
(692 pages)
4.EP2AGX45CU17C6N.pdf
(10 pages)
5.EP2AGX45CU17C6N.pdf
(88 pages)
6.EP2AGX190FF35C6N.pdf
(306 pages)
Specifications of EP2AGX190FF35C6N
Number Of Logic Elements/cells
181165
Number Of Labs/clbs
7612
Total Ram Bits
9939
Number Of I /o
612
Voltage - Supply
0.87 V ~ 0.93 V
Mounting Type
Surface Mount
Operating Temperature
0°C ~ 85°C
Package / Case
1152-FBGA
Family Name
Arria® II GX
Number Of Logic Blocks/elements
190300
# I/os (max)
612
Frequency (max)
400MHz
Operating Supply Voltage (typ)
900mV
Logic Cells
190300
Ram Bits
10380902.4
Operating Supply Voltage (min)
0.87V
Operating Supply Voltage (max)
0.93V
Operating Temp Range
0C to 85C
Operating Temperature Classification
Commercial
Mounting
Surface Mount
Pin Count
1152
Package Type
FC-FBGA
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Number Of Gates
-
Lead Free Status / Rohs Status
Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
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Chapter 4: DSP Blocks in Arria II Devices
Arria II Operational Mode Descriptions
Figure 4–20. Rounding and Saturation Locations
December 2010 Altera Corporation
1
16 User defined SAT Positions (bit 43-28)
43
43
Two saturation modes are supported in Arria II devices:
■
■
You must select one of the two options at compile time.
In 2’s complement format, the maximum negative number that can be represented is
–2
the maximum negative number to –2
■
■
Table 4–8
36-bits.
Table 4–8. Examples of Saturation
Arria II devices have up to 16 configurable bit positions out of the 44-bit bus ([43:0])
for the rounding and saturate logic unit, providing higher flexibility. You must select
the 16 configurable bit positions at compile time. These 16-bit positions are located at
bits [21:6] for rounding and [43:28] for saturation, as shown in
For symmetric saturation, the RND bit position is to determine where the LSP for the
saturated data is located.
You can use the rounding and saturation function as described in regular supported
multiplication operations shown in
type operations, the following convention is used.
The functionality of the rounding logic unit is in the format of:
Result = RND[
Likewise, the functionality of the saturation logic unit is in the format of:
Result = SAT[
(n-1)
42
42
Asymmetric saturation mode
Symmetric saturation mode
Asymmetric 32-bit saturation: Max = 0 × 7FFFFFFF, Min = 0 × 80000000
Symmetric 32-bit saturation: Max = 0 × 7FFFFFFF, Min = 0 × 80000001
44 to 36 Bits Saturation
, and the maximum positive number is 2
5926AC01342h
ADA38D2210h
lists how the saturation works. In this example, a 44-bit input is saturated to
∑
∑
(A × B)], when used for an accumulation type of operation.
(A × B)], when used for an accumulation type of operation.
29
28
16 User defined RND Positions (bit 21-6)
21
20
Symmetric SAT Result
Table 4–2 on page
Arria II Device Handbook Volume 1: Device Interfaces and Integration
800000001h
(n-1)
7FFFFFFFFh
+ 1. For example, for 32 bits:
(n-1)
7
– 1. Symmetrical saturation limits
6
4–7. However, for accumulation
Asymmetric SAT Result
1
0
0
800000000h
Figure
7FFFFFFFFh
4–20.
4–29
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