EP2AGX190FF35C6N Altera, EP2AGX190FF35C6N Datasheet - Page 241

• Manufacturer Part Number: EP2AGX190FF35C6N
• Description: IC ARRIA II GX 190K 1152FBGA
• Manufacturer: Altera
• Series: Arria II GXr

Specifications of EP2AGX190FF35C6N

• Number Of Logic Elements/cells: 181165
• Number Of Labs/clbs: 7612
• Total Ram Bits: 9939
• Number Of I /o: 612
• Voltage - Supply: 0.87 V ~ 0.93 V
• Mounting Type: Surface Mount
• Operating Temperature: 0°C ~ 85°C
• Package / Case: 1152-FBGA
• Family Name: Arria® II GX
• Number Of Logic Blocks/elements: 190300
• # I/os (max): 612
• Frequency (max): 400MHz
• Operating Supply Voltage (typ): 900mV
• Logic Cells: 190300
• Ram Bits: 10380902.4
• Operating Supply Voltage (min): 0.87V
• Operating Supply Voltage (max): 0.93V
• Operating Temp Range: 0C to 85C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 1152
• Package Type: FC-FBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of Gates: -
• Lead Free Status / Rohs Status: Compliant

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AIIGX51008-4.0
Arria II Device Handbook Volume 1: Device Interfaces and Integration
December 2010
December 2010
AIIGX51008-4.0
1
This chapter describes the high-speed differential I/O features and resources, the
functionality of the serializer/deserializer (SERDES), and the dynamic phase
alignment (DPA) circuitry in Arria
This chapter contains the following sections:
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Arria II devices have the following dedicated circuitry for high-speed differential I/O
support:
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Arria II devices support the following high-speed differential I/O standards:
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True mini-LVDS and RSDS inputs are not supported. The LVPECL I/O standard is
only used for phase-locked loop (PLL) clock inputs in differential mode.
“LVDS Channels” on page 8–2
“LVDS SERDES and DPA Block Diagram” on page 8–7
“Differential Transmitter” on page 8–8
“Differential Receiver” on page 8–11
“Programmable Pre-Emphasis and Programmable V
“Differential I/O Termination” on page 8–20
“PLLs” on page 8–21
“LVDS and DPA Clock Networks” on page 8–21
“Source-Synchronous Timing Budget” on page 8–23
“Differential Pin Placement Guidelines” on page 8–27
“Setting Up an LVDS Transmitter or Receiver Channel” on page 8–36
Differential I/O buffer
Transmitter serializer
Receiver deserializer
Data realignment block (bit slip)
DPA block
Synchronizer (FIFO buffer)
LVDS
mini-LVDS
RSDS
LVPECL
Bus LVDS (BLVDS) for Arria II GX devices
8. High-Speed Differential I/O Interfaces
®
II devices.
and DPA in Arria II Devices
OD
.” on page 8–10
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