EP2AGX190FF35C6N Altera, EP2AGX190FF35C6N Datasheet - Page 271

• Manufacturer Part Number: EP2AGX190FF35C6N
• Description: IC ARRIA II GX 190K 1152FBGA
• Manufacturer: Altera
• Series: Arria II GXr

Specifications of EP2AGX190FF35C6N

• Number Of Logic Elements/cells: 181165
• Number Of Labs/clbs: 7612
• Total Ram Bits: 9939
• Number Of I /o: 612
• Voltage - Supply: 0.87 V ~ 0.93 V
• Mounting Type: Surface Mount
• Operating Temperature: 0°C ~ 85°C
• Package / Case: 1152-FBGA
• Family Name: Arria® II GX
• Number Of Logic Blocks/elements: 190300
• # I/os (max): 612
• Frequency (max): 400MHz
• Operating Supply Voltage (typ): 900mV
• Logic Cells: 190300
• Ram Bits: 10380902.4
• Operating Supply Voltage (min): 0.87V
• Operating Supply Voltage (max): 0.93V
• Operating Temp Range: 0C to 85C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 1152
• Package Type: FC-FBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of Gates: -
• Lead Free Status / Rohs Status: Compliant

Chapter 8: High-Speed Differential I/O Interfaces and DPA in Arria II Devices
Differential Pin Placement Guidelines
December 2010 Altera Corporation
Using Both Corner PLLs in Arria II GX Devices
You can use both corner PLLs to drive DPA-enabled channels simultaneously, if they
drive the channels in their adjacent banks only. There must be at least one row of
separation between the two groups of DPA-enabled channels.
If one of the corner PLLs drives DPA-enabled channels in the upper and lower I/O
banks, you cannot use the center PLLs. You can use the other corner PLL to drive
DPA-enabled channels in their adjacent bank only. There must be at least one row of
separation between the two groups of DPA-enabled channels.
If the upper corner PLL drives DPA-enabled channels in the lower I/O bank, the
lower corner PLL cannot drive DPA-enabled channels in the upper I/O bank, and vice
versa. In other words, the corner PLLs cannot drive cross-banks simultaneously, as
shown in
Figure
8–26.
Arria II Device Handbook Volume 1: Device Interfaces and Integration
8–31