EP2AGX190FF35C6N Altera, EP2AGX190FF35C6N Datasheet - Page 121
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EP2AGX190FF35C6N
Manufacturer Part Number
EP2AGX190FF35C6N
Description
IC ARRIA II GX 190K 1152FBGA
Manufacturer
Altera
Series
Arria II GXr
Datasheets
1.EP2AGX45CU17C6N.pdf
(96 pages)
2.EP2AGX45CU17C6N.pdf
(14 pages)
3.EP2AGX45CU17C6N.pdf
(692 pages)
4.EP2AGX45CU17C6N.pdf
(10 pages)
5.EP2AGX45CU17C6N.pdf
(88 pages)
6.EP2AGX190FF35C6N.pdf
(306 pages)
Specifications of EP2AGX190FF35C6N
Number Of Logic Elements/cells
181165
Number Of Labs/clbs
7612
Total Ram Bits
9939
Number Of I /o
612
Voltage - Supply
0.87 V ~ 0.93 V
Mounting Type
Surface Mount
Operating Temperature
0°C ~ 85°C
Package / Case
1152-FBGA
Family Name
Arria® II GX
Number Of Logic Blocks/elements
190300
# I/os (max)
612
Frequency (max)
400MHz
Operating Supply Voltage (typ)
900mV
Logic Cells
190300
Ram Bits
10380902.4
Operating Supply Voltage (min)
0.87V
Operating Supply Voltage (max)
0.93V
Operating Temp Range
0C to 85C
Operating Temperature Classification
Commercial
Mounting
Surface Mount
Pin Count
1152
Package Type
FC-FBGA
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Number Of Gates
-
Lead Free Status / Rohs Status
Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
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Chapter 5: Clock Networks and PLLs in Arria II Devices
Clock Networks in Arria II Devices
Figure 5–13. clkena Signals for Arria II Devices
Note to
(1) You can use the clkena signals to enable or disable the GCLK and RCLK networks or the PLL<#>_CLKOUT pins.
December 2010 Altera Corporation
gate with R2 not bypassed
Figure
gate with R2 bypassed
Clock Source Control for PLLs
select multiplexer
5–13:
output of AND
output of AND
output of
clkena
clock
In Arria II devices, the clkena signals are supported at the clock network level instead
of at the PLL output counter level. This allows you to gate off the clock even when a
PLL is not used. You can also use the clkena signals to control the dedicated external
clocks from the PLLs. Arria II devices also have an additional metastability register
that aids in asynchronous enable or disable of the GCLK and RCLK networks. You
can optionally bypass this register in the Quartus II software.
Figure 5–13
signal is synchronous to the falling edge of the clock output.
The PLL can remain locked independent of the clkena signals because the
loop-related counters are not affected. This feature is useful for applications that
require a low power or sleep mode. The clkena signal can also disable clock outputs if
the system is not tolerant of frequency over-shoot during resynchronization.
The clock input to Arria II PLLs comes from clock input multiplexers. The clock
multiplexer inputs come from dedicated clock input pins, PLLs through the GCLK
and RCLK networks, or from dedicated connections between adjacent corner and
center PLLs (Arria II GX devices) or from dedicated connections between adjacent
top/bottom and left/right PLLs (Arria II GZ devices). For Arria II GX devices, the
clock input sources to corner (PLL_1, PLL_2, PLL_3, PLL_4) and center PLLs (PLL_5 and
PLL_6) are shown in
top/bottom and left/right PLLs (L2, L3, T1, T2, B1, B2, R2, and R3) are shown in
Figure
The multiplexer select lines are set in the configuration file only. When configured,
you cannot change this block without loading a new .sof or .pof. The Quartus II
software automatically sets the multiplexer select signals depending on the clock
sources selected in your design.
5–15.
shows a waveform example for the clock output enable. The clkena
Figure
5–14. For Arria II GZ devices, the clock input sources to
Arria II Device Handbook Volume 1: Device Interfaces and Integration
5–17
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