EP2AGX190FF35C6N Altera, EP2AGX190FF35C6N Datasheet - Page 169
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EP2AGX190FF35C6N
Manufacturer Part Number
EP2AGX190FF35C6N
Description
IC ARRIA II GX 190K 1152FBGA
Manufacturer
Altera
Series
Arria II GXr
Datasheets
1.EP2AGX45CU17C6N.pdf
(96 pages)
2.EP2AGX45CU17C6N.pdf
(14 pages)
3.EP2AGX45CU17C6N.pdf
(692 pages)
4.EP2AGX45CU17C6N.pdf
(10 pages)
5.EP2AGX45CU17C6N.pdf
(88 pages)
6.EP2AGX190FF35C6N.pdf
(306 pages)
Specifications of EP2AGX190FF35C6N
Number Of Logic Elements/cells
181165
Number Of Labs/clbs
7612
Total Ram Bits
9939
Number Of I /o
612
Voltage - Supply
0.87 V ~ 0.93 V
Mounting Type
Surface Mount
Operating Temperature
0°C ~ 85°C
Package / Case
1152-FBGA
Family Name
Arria® II GX
Number Of Logic Blocks/elements
190300
# I/os (max)
612
Frequency (max)
400MHz
Operating Supply Voltage (typ)
900mV
Logic Cells
190300
Ram Bits
10380902.4
Operating Supply Voltage (min)
0.87V
Operating Supply Voltage (max)
0.93V
Operating Temp Range
0C to 85C
Operating Temperature Classification
Commercial
Mounting
Surface Mount
Pin Count
1152
Package Type
FC-FBGA
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Number Of Gates
-
Lead Free Status / Rohs Status
Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
- EP2AGX45CU17C6N PDF datasheet
- EP2AGX45CU17C6N PDF datasheet #2
- EP2AGX45CU17C6N PDF datasheet #3
- EP2AGX45CU17C6N PDF datasheet #4
- EP2AGX45CU17C6N PDF datasheet #5
- EP2AGX190FF35C6N PDF datasheet #6
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Chapter 6: I/O Features in Arria II Devices
I/O Structure
Figure 6–3. IOE Structure for Arria II GX Devices
December 2010 Altera Corporation
Write
Data
Core
To
Core
To
Core
form
Read
Data
to
Core
OE
from
Core
DQS
CQn
clkin
I/O registers are composed of the input path for handling data from the pin to the
core, the output path for handling data from the core to the pin, and the output enable
path for handling the OE signal to the output buffer. These registers allow faster
source-synchronous register-to-register transfers and resynchronization. You can
bypass each block of the output and output enable paths.
show the Arria II IOE structure.
to internal Cells
Input Pin Delay
Synchronization
Registers
Input Register Delay
DQS Bus
to
Output Register
Output Register
OE Register
OE Register
D
D
D
D
PRN
PRN
PRN
PRN
Q
Q
Q
Q
to Input Register
Input Pin Delay
Input Register
Input Register
D
D
PRN
PRN
Q
Q
Arria II Device Handbook Volume 1: Device Interfaces and Integration
Output Pin
Delay
Output Enable
Input Register
Programmable
D
Pin Delay
Strength and
Slew Rate
PRN
Current
Control
Q
Open Drain
Output Buffer
Input Buffer
PCI Clamp
Figure 6–3
V
CCIO
V
CCIO
Pull-Up Resistor
Programmable
Termination
Calobration
From OCT
On-Chip
and
Bus-Hold
Block
Circuit
Figure 6–4
6–11
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