EP2AGX190FF35C6N Altera, EP2AGX190FF35C6N Datasheet - Page 432
![no-image](/images/manufacturer_photos/0/0/40/altera_sml.jpg)
EP2AGX190FF35C6N
Manufacturer Part Number
EP2AGX190FF35C6N
Description
IC ARRIA II GX 190K 1152FBGA
Manufacturer
Altera
Series
Arria II GXr
Datasheets
1.EP2AGX45CU17C6N.pdf
(96 pages)
2.EP2AGX45CU17C6N.pdf
(14 pages)
3.EP2AGX45CU17C6N.pdf
(692 pages)
4.EP2AGX45CU17C6N.pdf
(10 pages)
5.EP2AGX45CU17C6N.pdf
(88 pages)
6.EP2AGX190FF35C6N.pdf
(306 pages)
Specifications of EP2AGX190FF35C6N
Number Of Logic Elements/cells
181165
Number Of Labs/clbs
7612
Total Ram Bits
9939
Number Of I /o
612
Voltage - Supply
0.87 V ~ 0.93 V
Mounting Type
Surface Mount
Operating Temperature
0°C ~ 85°C
Package / Case
1152-FBGA
Family Name
Arria® II GX
Number Of Logic Blocks/elements
190300
# I/os (max)
612
Frequency (max)
400MHz
Operating Supply Voltage (typ)
900mV
Logic Cells
190300
Ram Bits
10380902.4
Operating Supply Voltage (min)
0.87V
Operating Supply Voltage (max)
0.93V
Operating Temp Range
0C to 85C
Operating Temperature Classification
Commercial
Mounting
Surface Mount
Pin Count
1152
Package Type
FC-FBGA
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Number Of Gates
-
Lead Free Status / Rohs Status
Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
- EP2AGX45CU17C6N PDF datasheet
- EP2AGX45CU17C6N PDF datasheet #2
- EP2AGX45CU17C6N PDF datasheet #3
- EP2AGX45CU17C6N PDF datasheet #4
- EP2AGX45CU17C6N PDF datasheet #5
- EP2AGX190FF35C6N PDF datasheet #6
- Current page: 432 of 692
- Download datasheet (22Mb)
1–46
Table 1–14. RX Phase Compensation FIFO Modes for Arria II Devices
Arria II Device Handbook Volume 2: Transceivers
Low Latency
High-Latency
Register
Note to
(1) Pending characterization.
Table
Mode
1–14:
RX Phase Compensation FIFO
The RX phase compensation FIFO in each channel ensures reliable transfer of data
and status signals between the receiver channel and the FPGA fabric. The RX phase
compensation FIFO compensates for the phase difference between the parallel
receiver PCS clock (FIFO write clock) and the FPGA fabric clock (FIFO read clock).
Table 1–14
automatically sets the mode that applies to a particular functional mode.
Figure 1–46
and read clock to the FIFO are at half-rate if the byte serializer is used in the
configuration.
Figure 1–46. RX Phase Compensation FIFO Block Diagram
Notes to
(1) The tx_clkout clock is from the transmitter channel clock divider and is used in non-bonded configurations with
(2) The rx_clkout clock is from the receiver channel CDR and is used in non-bonded configurations that does not use
(3) The coreclkout clock is from the CMU0 block of the associated transceiver block or the master transceiver block for
(4) Use this clock for the FIFO read clock if you instantiate the rx_coreclk port in the ALTGX MegaWizard Plug-In
(5) The rx_phase_comp_fifo_error is optional and available in all functional modes. This signal is asserted high to
into the LSByte position after a rising edge on the rx_enabyteord signal. If the byte
ordering blocks find the first data byte that matches the programmed byte
ordering pattern in the LSByte position of the byte-deserialized data, it considers
the data to be byte ordered and does not insert any PAD byte. In either case, the
byte ordering block asserts the rx_byteorderalignstatus signal.
4-words deep
8-words deep
the rate match FIFO.
the rate match FIFO.
×4 bonded or ×8 bonded channel configurations, respectively.
Manager, regardless of the channel configurations. Otherwise, use the same clock used for the write clock for the
read clock.
indicate an overflow or underflow condition.
FIFO Depth
Figure
coreclkout (3)
—
tx_clkout (1)
rx_clkout (2)
lists the RX phase compensation FIFO modes. The Quartus II software
shows the RX phase compensation FIFO block diagram. The write clock
1–46:
rx_coreclk (4)
2-to-3 parallel clock cycles
4-to-5 parallel clock cycles
Latency Through FIFO
Data from the Byte
Ordering, Byte
Deserialization,
or 8B/10B Decoder
1
Write Clock
Compensation
(1)
(1)
Phase
FIFO
Chapter 1: Transceiver Architecture in Arria II Devices
RX
Read Clock
All functional modes except PCIe and
Applicable Functional Modes
rx_dataout to the FPGA fabric
rx_phase_comp_fifo_error (5)
Deterministic Latency
Deterministic Latency
December 2010 Altera Corporation
PCIe
Receiver Channel Datapath
Related parts for EP2AGX190FF35C6N
Image
Part Number
Description
Manufacturer
Datasheet
Request
R
![DK-CYCII-2C20N](/photos/9/20/92074/mfgdk-cycii-2c20nboard_tmb.jpg)
Part Number:
Description:
CYCLONE II STARTER KIT EP2C20N
Manufacturer:
Altera
Datasheet:
![EP610PC-35](/images/manufacturer_photos/0/0/41/altera_corporation_tmb.jpg)
Part Number:
Description:
CPLD, EP610 Family, ECMOS Process, 300 Gates, 16 Macro Cells, 16 Reg., 16 User I/Os, 5V Supply, 35 Speed Grade, 24DIP
Manufacturer:
Altera Corporation
Datasheet:
![EP610PC-15](/images/manufacturer_photos/0/0/41/altera_corporation_tmb.jpg)
Part Number:
Description:
CPLD, EP610 Family, ECMOS Process, 300 Gates, 16 Macro Cells, 16 Reg., 16 User I/Os, 5V Supply, 15 Speed Grade, 24DIP
Manufacturer:
Altera Corporation
Datasheet:
![EP610IPC-25](/images/manufacturer_photos/0/0/41/altera_corporation_tmb.jpg)
Part Number:
Description:
Manufacturer:
Altera Corporation
Datasheet:
![EP610PC-30](/images/manufacturer_photos/0/0/41/altera_corporation_tmb.jpg)
Part Number:
Description:
CPLD, EP610 Family, ECMOS Process, 300 Gates, 16 Macro Cells, 16 Reg., 16 User I/Os, 5V Supply, 30 Speed Grade, 24DIP
Manufacturer:
Altera Corporation
Datasheet:
![EP220PC-10](/images/manufacturer_photos/0/0/41/altera_corporation_tmb.jpg)
Part Number:
Description:
High-performance, low-power erasable programmable logic devices with 8 macrocells, 10ns
Manufacturer:
Altera Corporation
Datasheet:
![EP220PC-7](/images/manufacturer_photos/0/0/41/altera_corporation_tmb.jpg)
Part Number:
Description:
High-performance, low-power erasable programmable logic devices with 8 macrocells, 7ns
Manufacturer:
Altera Corporation
Datasheet:
![EP220PC-12](/images/manufacturer_photos/0/0/41/altera_corporation_tmb.jpg)
Part Number:
Description:
Classic EPLD
Manufacturer:
Altera Corporation
Datasheet:
![EP220PC-10A](/images/manufacturer_photos/0/0/41/altera_corporation_tmb.jpg)
Part Number:
Description:
High-performance, low-power erasable programmable logic devices with 8 macrocells, 10ns
Manufacturer:
Altera Corporation
Datasheet:
![P85C224-66](/images/manufacturer_photos/0/0/41/altera_corporation_tmb.jpg)
Part Number:
Description:
Manufacturer:
Altera Corporation
Datasheet:
![EP320PC](/images/manufacturer_photos/0/0/41/altera_corporation_tmb.jpg)
Part Number:
Description:
Manufacturer:
Altera Corporation
Datasheet:
![EP2A15B724C7](/images/manufacturer_photos/0/0/41/altera_corporation_tmb.jpg)
Part Number:
Description:
Manufacturer:
Altera Corporation
Datasheet:
![EP610PC-25T](/images/manufacturer_photos/0/0/41/altera_corporation_tmb.jpg)
Part Number:
Description:
CPLD, EP610 Family, ECMOS Process, 300 Gates, 16 Macro Cells, 16 Reg., 16 User I/Os, 5V Supply, 25 Speed Grade, 24DIP
Manufacturer:
Altera Corporation
Datasheet: