EP2AGX190FF35C6N Altera, EP2AGX190FF35C6N Datasheet - Page 498

• Manufacturer Part Number: EP2AGX190FF35C6N
• Description: IC ARRIA II GX 190K 1152FBGA
• Manufacturer: Altera
• Series: Arria II GXr

Specifications of EP2AGX190FF35C6N

• Number Of Logic Elements/cells: 181165
• Number Of Labs/clbs: 7612
• Total Ram Bits: 9939
• Number Of I /o: 612
• Voltage - Supply: 0.87 V ~ 0.93 V
• Mounting Type: Surface Mount
• Operating Temperature: 0°C ~ 85°C
• Package / Case: 1152-FBGA
• Family Name: Arria® II GX
• Number Of Logic Blocks/elements: 190300
• # I/os (max): 612
• Frequency (max): 400MHz
• Operating Supply Voltage (typ): 900mV
• Logic Cells: 190300
• Ram Bits: 10380902.4
• Operating Supply Voltage (min): 0.87V
• Operating Supply Voltage (max): 0.93V
• Operating Temp Range: 0C to 85C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 1152
• Package Type: FC-FBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of Gates: -
• Lead Free Status / Rohs Status: Compliant

2–8
Figure 2–5. Transmitter Datapath Clocking in a Non-Bonded Configuration
Arria II Device Handbook Volume 2: Transceivers
Fabric
FPGA
hard IP
hard IP
hard IP
hard IP
PCIe
PCIe
PCIe
PCIe
Figure 2–5
configuration.
Interface
Interface
Interface
Interface
PIPE
PIPE
PIPE
PIPE
shows the transmitter channel datapath clocking in a non-bonded
Channel3
Channel2
Channel1
Channel0
tx_clkout[3]
tx_clkout[2]
tx_clkout[1]
tx_clkout[0]
Compensation
wrclk
Compensation
wrclk
Compensation
wrclk
Compensation
wrclk
TX Phase
TX Phase
TX Phase
TX Phase
FIFO
FIFO
FIFO
FIFO
rdclk
rdclk
rdclk
rdclk
Input Reference Clock
Input Reference Clock
wrclk
wrclk
wrclk
wrclk
Byte Serializer
Byte Serializer
Byte Serializer
Byte Serializer
Transmitter Channel PCS
/2
Transmitter Channel PCS
/2
Transmitter Channel PCS
/2
Transmitter Channel PCS
/2
rdclk
rdclk
rdclk
rdclk
CMU1_PLL
CMU0_PLL
Chapter 2: Transceiver Clocking in Arria II Devices
8B/10B Encoder
8B/10B Encoder
8B/10B Encoder
8B/10B Encoder
CMU1 Clock Divider
CMU0 Clock Divider
CMU1_Channel
CMU0_Channel
Transceiver Channel Datapath Clocking
December 2010 Altera Corporation
FPGA Fabric-Transceiver Interface Clock
High-Speed Serial Clock
Low-Speed Parallel Clock
Divider Block
Divider Block
Divider Block
Divider Block
Local Clock
Local Clock
Local Clock
Local Clock
Transmitter Channel
Transmitter Channel
Transmitter Channel
Transmitter Channel
PMA
PMA
PMA
PMA