XCV50E-6PQ240I Xilinx Inc, XCV50E-6PQ240I Datasheet - Page 135
![no-image](/images/no-image-200.jpg)
XCV50E-6PQ240I
Manufacturer Part Number
XCV50E-6PQ240I
Description
IC FPGA 1.8V I-TEMP 240-PQFP
Manufacturer
Xilinx Inc
Series
Virtex™-Er
Datasheet
1.XCV50E-6PQ240I.pdf
(233 pages)
Specifications of XCV50E-6PQ240I
Number Of Logic Elements/cells
1728
Number Of Labs/clbs
384
Total Ram Bits
65536
Number Of I /o
158
Number Of Gates
71693
Voltage - Supply
1.71 V ~ 1.89 V
Mounting Type
Surface Mount
Operating Temperature
-40°C ~ 100°C
Package / Case
240-BFQFP
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
XCV50E-6PQ240I
Manufacturer:
XilinxInc
Quantity:
3 000
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Table 16: FG256 Package — XCV50E, XCV100E,
XCV200E, XCV300E
DS022-4 (v2.5) March 14, 2003
Production Product Specification
Notes:
1.
2.
Bank
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
V
otherwise, I/O option only.
V
I/O option only.
REF
REF
or I/O option only in the XCV100E, 200E, 300E;
or I/O option only in the XCV200E, 300E; otherwise,
R
Pin Description
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
Pin #
H10
G11
G10
K11
K10
F11
F10
B15
A16
J10
G9
G8
G7
G6
K9
K8
K7
K6
H9
H8
H7
F7
F6
B2
A1
J9
J8
J7
www.xilinx.com
1-800-255-7778
FG256 Differential Pin Pairs
Virtex-E devices have differential pin pairs that can also pro-
vide other functions when not used as a differential pair. A √
in the AO column indicates that the pin pair can be used as
an asynchronous output for all devices provided in this
package. Pairs with a note number in the AO column are
device dependent. They can have asynchronous outputs if
the pin pair are in the same CLB row and column in the
device. Numbers in this column refer to footnotes that indi-
cate which devices have pin pairs than can be asynchro-
nous outputs. The Other Functions column indicates
alternative function(s) not available when the pair is used as
a differential pair or differential clock.
Table 17: FG256 Differential Pin Pair Summary
XCV50E, XCV100E, XCV200E, XCV300E
Pair
10
11
12
13
14
15
16
17
18
0
1
2
3
0
1
2
3
4
5
6
7
8
9
Virtex™-E 1.8 V Field Programmable Gate Arrays
Total Pairs: 83, Asynchronous Outputs: 35
Bank
4
5
1
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
1
1
Global Differential Clock
D10
D11
C11
D12
C12
A11
E11
B13
Pin
N8
R8
C9
B8
A3
E6
A4
B5
A5
C7
C8
A6
A8
A9
B9
P
IO LVDS
C10
C13
E10
A10
B11
A12
A13
B12
A14
Pin
N9
T8
A8
A7
C5
D5
B4
D6
C6
B6
D7
B7
A7
D9
N
AO
NA
NA
NA
NA
NA
7
√
√
2
√
√
1
1
2
1
1
√
√
2
√
√
7
√
IO_DLL_L52N
IO_LVDS_DLL
IO_DLL_L52P
IO_DLL_L8N
IO_DLL_L8P
Functions
Module 4 of 4
Other
VREF
VREF
VREF
VREF
VREF
VREF
VREF
VREF
CS
-
-
-
-
-
-
-
-
-
49
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