XCV50E-6PQ240I Xilinx Inc, XCV50E-6PQ240I Datasheet - Page 22

• Manufacturer Part Number: XCV50E-6PQ240I
• Description: IC FPGA 1.8V I-TEMP 240-PQFP
• Manufacturer: Xilinx Inc
• Series: Virtex™-Er

Specifications of XCV50E-6PQ240I

• Number Of Logic Elements/cells: 1728
• Number Of Labs/clbs: 384
• Total Ram Bits: 65536
• Number Of I /o: 158
• Number Of Gates: 71693
• Voltage - Supply: 1.71 V ~ 1.89 V
• Mounting Type: Surface Mount
• Operating Temperature: -40°C ~ 100°C
• Package / Case: 240-BFQFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant

Virtex™-E 1.8 V Field Programmable Gate Arrays
Table 11: SelectMAP Write Timing Characteristics
A flowchart for the write operation is shown in
Note that if CCLK is slower than f
asserts BUSY, In this case, the above handshake is unnec-
essary, and data can simply be entered into the FPGA every
CCLK cycle.
Abort
During a given assertion of CS, the user cannot switch from
a write to a read, or vice-versa. This action causes the cur-
Module 2 of 4
16
CCLK
D
CS Setup/Hold
WRITE Setup/Hold
BUSY Propagation Delay
Maximum Frequency
Maximum Frequency with no handshake
0-7
Setup/Hold
DATA[0:7]
WRITE
BUSY
CCLK
CS
Description
5
No Write
3
CCNH
1
, the FPGA never
7
Figure 17: Write Operations
Figure
1/2
3/4
5/6
www.xilinx.com
1-800-255-7778
7
Write
18.
2
rent packet command to be aborted. The device remains
BUSY until the aborted operation has completed. Following
an abort, data is assumed to be unaligned to word bound-
aries, and the FPGA requires a new synchronization word
prior to accepting any new packets.
To initiate an abort during a write operation, de-assert
WRITE. At the rising edge of CCLK, an abort is initiated, as
shown in
T
T
T
SMCSCC
SMCCW
SMDCC
No Write
T
Symbol
F
SMCKBY
Figure
F
CCNH
CC
/T
/T
/T
SMCCD
SMCCCS
SMWCC
19.
Write
Production Product Specification
4
6
DS022-2 (v2.6.1) June 15, 2004
5.0 / 1.7
7.0 / 1.7
7.0 / 1.7
DS022_45_071702
12.0
66
50
MHz, max
MHz, max
ns, max
ns, min
ns, min
ns, min
Units
R