XCV50E-6PQ240I Xilinx Inc, XCV50E-6PQ240I Datasheet - Page 15

• Manufacturer Part Number: XCV50E-6PQ240I
• Description: IC FPGA 1.8V I-TEMP 240-PQFP
• Manufacturer: Xilinx Inc
• Series: Virtex™-Er

Specifications of XCV50E-6PQ240I

• Number Of Logic Elements/cells: 1728
• Number Of Labs/clbs: 384
• Total Ram Bits: 65536
• Number Of I /o: 158
• Number Of Gates: 71693
• Voltage - Supply: 1.71 V ~ 1.89 V
• Mounting Type: Surface Mount
• Operating Temperature: -40°C ~ 100°C
• Package / Case: 240-BFQFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant

Instruction Set
The Virtex-E series boundary-scan instruction set also
includes instructions to configure the device and read back
configuration data (CFG_IN, CFG_OUT, and JSTART). The
complete instruction set is coded as shown in
Table 6: Boundary Scan Instructions
DS022-2 (v2.6.1) June 15, 2004
Production Product Specification
EXTEST
SAMPLE/
PRELOAD
USER1
USER2
CFG_OUT
Boundary-Scan
Command
R
TDI
Code(4:0)
IOB
IOB
IOB
IOB
IOB
IOB
IOB
Binary
00000
00001
00010
00011
00100
IOB
INSTRUCTION REGISTER
IOB
REGISTER
Enables boundary-scan
EXTEST operation
Enables boundary-scan
SAMPLE/PRELOAD
operation
Access user-defined
register 1
Access user-defined
register 2
Access the
configuration bus for
read operations.
BYPASS
IOB
Figure 11: Virtex-E Family Boundary Scan Logic
IOB
Description
IOB
Table
IOB
IOB
IOB
IOB
IOB
IOB
IOB
M
U
X
TDO
6..
www.xilinx.com
1-800-255-7778
IOB.Q
IOB.T
IOB.T
IOB.I
IOB.I
CAPTURE
SHIFT/
Table 6: Boundary Scan Instructions (Continued)
DATAOUT
CFG_IN
INTEST
USERCODE
IDCODE
HIGHZ
JSTART
BYPASS
RESERVED
Boundary-Scan
DATA IN
Command
CLOCK DATA
1
0
1
0
1
0
1
0
1
0
REGISTER
Virtex™-E 1.8 V Field Programmable Gate Arrays
D
D
D
D
D
Q
Q
Q
Q
Q
UPDATE
D
D
D
D
D
LE
LE
LE
LE
LE
Code(4:0)
All other
sd
sd
sd
sd
sd
Binary
00101
00111
01000
01001
01010
01100
11111
codes
Q
Q
Q
Q
Q
0
1
1
0
1
0
0
1
1
0
EXTEST
Access the
configuration bus for
write operations.
Enables boundary-scan
INTEST operation
Enables shifting out
USER code
Enables shifting out of
ID Code
3-states output pins
while enabling the
Bypass Register
Clock the start-up
sequence when
StartupClk is TCK
Enables BYPASS
Xilinx reserved
instructions
X9016
Description
Module 2 of 4
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