XCV50E-6PQ240I Xilinx Inc, XCV50E-6PQ240I Datasheet - Page 145

• Manufacturer Part Number: XCV50E-6PQ240I
• Description: IC FPGA 1.8V I-TEMP 240-PQFP
• Manufacturer: Xilinx Inc
• Series: Virtex™-Er

Specifications of XCV50E-6PQ240I

• Number Of Logic Elements/cells: 1728
• Number Of Labs/clbs: 384
• Total Ram Bits: 65536
• Number Of I /o: 158
• Number Of Gates: 71693
• Voltage - Supply: 1.71 V ~ 1.89 V
• Mounting Type: Surface Mount
• Operating Temperature: -40°C ~ 100°C
• Package / Case: 240-BFQFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant

Table 19: FG456 Differential Pin Pair Summary
XCV200E, XCV300E
DS022-4 (v2.5) March 14, 2003
Production Product Specification
Notes:
1.
2.
Pair
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
88
89
90
91
92
93
94
95
96
97
98
99
AO in the XCV200E.
AO in the XCV300E.
Bank
5
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
R
Pin
W1
M4
M6
U4
U2
U1
R1
N5
N4
N2
H1
H3
H4
G3
G5
D2
C1
V7
Y2
V3
V1
T1
P3
K2
K3
K5
F2
E2
L4
L1
J2
P
AB3
Pin
W3
M3
G1
V4
Y1
V2
R5
R4
R2
P5
P2
P1
N3
N1
K4
K1
H2
H5
E1
E3
T3
T5
L3
L5
L6
F1
F3
F5
J3
J5
N
AO
√
√
√
√
√
√
2
1
2
√
√
√
2
1
2
√
√
√
2
2
√
√
√
√
2
2
√
√
√
√
√
Functions
Other
VREF
VREF
VREF
VREF
VREF
VREF
VREF
VREF
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
www.xilinx.com
1-800-255-7778
FG676 Fine-Pitch Ball Grid Array Package
XCV400E and XCV600E devices in the FG676 fine-pitch
Ball Grid Array package have footprint compatibility. Pins
labeled I0_VREF can be used as either in all parts unless
device-dependent as indicated in the footnotes. If the pin is
not used as V
ately following
information.
Table 20: FG676 — XCV400E, XCV600E
Bank
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Virtex™-E 1.8 V Field Programmable Gate Arrays
REF
Table
, it can be used as general I/O. Immedi-
IO_VREF_L2N_YY
IO_VREF_L5N_YY
IO_VREF_L8N_Y
Pin Description
20, see
IO_L1N_YY
IO_L1P_YY
IO_L2P_YY
IO_L5P_YY
IO_L6N_YY
IO_L6P_YY
IO_L0N_Y
IO_L7N_Y
IO_L0P_Y
IO_L7P_Y
IO_L8P_Y
IO_L3N
IO_L4N
IO_L3P
IO_L4P
GCK3
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
Table 21
for Differential Pair
Module 4 of 4
Pin #
A10
B12
D13
G13
E13
A9
B4
B7
G8
G9
A6
B3
C6
C8
D5
C4
C5
D6
E7
A4
B5
D7
E8
A5
D8
C7
E9
F7
F8
F9
1
1
2
1
1
1
59