XCV50E-6PQ240I Xilinx Inc, XCV50E-6PQ240I Datasheet - Page 36
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XCV50E-6PQ240I
Manufacturer Part Number
XCV50E-6PQ240I
Description
IC FPGA 1.8V I-TEMP 240-PQFP
Manufacturer
Xilinx Inc
Series
Virtex™-Er
Datasheet
1.XCV50E-6PQ240I.pdf
(233 pages)
Specifications of XCV50E-6PQ240I
Number Of Logic Elements/cells
1728
Number Of Labs/clbs
384
Total Ram Bits
65536
Number Of I /o
158
Number Of Gates
71693
Voltage - Supply
1.71 V ~ 1.89 V
Mounting Type
Surface Mount
Operating Temperature
-40°C ~ 100°C
Package / Case
240-BFQFP
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Available stocks
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Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
XCV50E-6PQ240I
Manufacturer:
XilinxInc
Quantity:
3 000
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R
Virtex™-E 1.8 V Field Programmable Gate Arrays
VHDL Initialization Example
library IEEE;
use IEEE.std_logic_1164.all;
entity MYMEM is
port (CLK, WE:in std_logic;
ADDR: in std_logic_vector(8 downto 0);
DIN: in std_logic_vector(7 downto 0);
DOUT: out std_logic_vector(7 downto 0));
end MYMEM;
architecture BEHAVE of MYMEM is
signal logic0, logic1: std_logic;
component RAMB4_S8
--synopsys translate_off
generic( INIT_00,INIT_01, INIT_02, INIT_03, INIT_04, INIT_05, INIT_06, INIT_07,
INIT_08, INIT_09, INIT_0a, INIT_0b, INIT_0c, INIT_0d, INIT_0e, INIT_0f : BIT_VECTOR(255
downto 0)
:= X"0000000000000000000000000000000000000000000000000000000000000000");
--synopsys translate_on
port (WE, EN, RST, CLK: in STD_LOGIC;
ADDR: in STD_LOGIC_VECTOR(8 downto 0);
DI: in STD_LOGIC_VECTOR(7 downto 0);
DO: out STD_LOGIC_VECTOR(7 downto 0));
end component;
--synopsys dc_script_begin
--set_attribute ram0 INIT_00
"0123456789ABCDEF0123456789ABCDEF0123456789ABCDEF0123456789ABCDEF" -type string
--set_attribute ram0 INIT_01
"FEDCBA9876543210FEDCBA9876543210FEDCBA9876543210FEDCBA9876543210" -type string
--synopsys dc_script_end
begin
logic0 <=’0’;
logic1 <=’1’;
ram0: RAMB4_S8
--synopsys translate_off
generic map (
INIT_00 => X"0123456789ABCDEF0123456789ABCDEF0123456789ABCDEF0123456789ABCDEF",
INIT_01 => X"FEDCBA9876543210FEDCBA9876543210FEDCBA9876543210FEDCBA9876543210")
--synopsys translate_on
port map (WE=>WE, EN=>logic1, RST=>logic0, CLK=>CLK,ADDR=>ADDR, DI=>DIN, DO=>DOUT);
end BEHAVE;
Module 2 of 4
www.xilinx.com
DS022-2 (v2.6.1) June 15, 2004
30
1-800-255-7778
Production Product Specification
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