XCV50E-6PQ240I Xilinx Inc, XCV50E-6PQ240I Datasheet - Page 18

• Manufacturer Part Number: XCV50E-6PQ240I
• Description: IC FPGA 1.8V I-TEMP 240-PQFP
• Manufacturer: Xilinx Inc
• Series: Virtex™-Er

Specifications of XCV50E-6PQ240I

• Number Of Logic Elements/cells: 1728
• Number Of Labs/clbs: 384
• Total Ram Bits: 65536
• Number Of I /o: 158
• Number Of Gates: 71693
• Voltage - Supply: 1.71 V ~ 1.89 V
• Mounting Type: Surface Mount
• Operating Temperature: -40°C ~ 100°C
• Package / Case: 240-BFQFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant

Virtex™-E 1.8 V Field Programmable Gate Arrays
For in-circuit debugging, an optional download and read-
back cable is available. This cable connects the FPGA in the
target system to a PC or workstation. After downloading the
design into the FPGA, the designer can single-step the
Configuration
Virtex-E devices are configured by loading configuration
data into the internal configuration memory. Note that
attempting to load an incorrect bitstream causes configura-
tion to fail and can damage the device.
Some of the pins used for configuration are dedicated pins,
while others can be re-used as general purpose inputs and
outputs once configuration is complete.
The following are dedicated pins:
•
•
•
•
•
Depending on the configuration mode chosen, CCLK can
be an output generated by the FPGA, or can be generated
externally and provided to the FPGA as an input. The
PROGRAM pin must be pulled High prior to reconfiguration.
Note that some configuration pins can act as outputs. For
correct operation, these pins require a V
2.5 V. At 3.3 V the pins operate as LVTTL, and at 2.5 V they
Table 8: Configuration Codes
Module 2 of 4
12
Master-serial mode
Boundary-scan mode
SelectMAP mode
Slave-serial mode
Master-serial mode
Boundary-scan mode
SelectMAP mode
Slave-serial mode
Configuration Mode
Mode pins (M2, M1, M0)
Configuration clock pin (CCLK)
PROGRAM pin
DONE pin
Boundary-scan pins (TDI, TDO, TMS, TCK)
M2
0
1
1
1
1
0
0
0
M1
0
0
1
1
0
0
1
1
M0
0
1
0
1
0
1
0
1
CCO
CCLK Direction
of 3.3 V or
Out
N/A
Out
N/A
In
In
In
In
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logic, readback the contents of the flip-flops, and so observe
the internal logic state. Simple modifications can be down-
loaded into the system in a matter of minutes.
operate as LVCMOS. All affected pins fall in banks 2 or 3.
The configuration pins needed for SelectMap (CS, Write)
are located in bank 1.
Configuration Modes
Virtex-E supports the following four configuration modes.
•
•
•
•
The Configuration mode pins (M2, M1, M0) select among
these configuration modes with the option in each case of
having the IOB pins either pulled up or left floating prior to
configuration. The selection codes are listed in
Configuration through the boundary-scan port is always
available, independent of the mode selection. Selecting the
boundary-scan mode simply turns off the other modes. The
three mode pins have internal pull-up resistors, and default
to a logic High if left unconnected. However, it is recom-
mended to drive the configuration mode pins externally.
Data Width
Slave-serial mode
Master-serial mode
SelectMAP mode
Boundary-scan mode (JTAG)
1
1
8
1
1
1
8
1
Serial D
Yes
Yes
Yes
Yes
No
No
No
No
out
Production Product Specification
DS022-2 (v2.6.1) June 15, 2004
Configuration Pull-ups
Yes
Yes
Yes
Yes
No
No
No
No
Table
8.
R