XCV50E-6PQ240I Xilinx Inc, XCV50E-6PQ240I Datasheet - Page 90

• Manufacturer Part Number: XCV50E-6PQ240I
• Description: IC FPGA 1.8V I-TEMP 240-PQFP
• Manufacturer: Xilinx Inc
• Series: Virtex™-Er

Specifications of XCV50E-6PQ240I

• Number Of Logic Elements/cells: 1728
• Number Of Labs/clbs: 384
• Total Ram Bits: 65536
• Number Of I /o: 158
• Number Of Gates: 71693
• Voltage - Supply: 1.71 V ~ 1.89 V
• Mounting Type: Surface Mount
• Operating Temperature: -40°C ~ 100°C
• Package / Case: 240-BFQFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant

Virtex™-E 1.8 V Field Programmable Gate Arrays
CS144 Chip-Scale Package
XCV50E, XCV100E, XCV200E, XCV300E and XCV400E
devices in CS144 Chip-scale packages have footprint com-
patibility. In the CS144 package, bank pairs that share a
side are internally interconnected, permitting four choices
for V
Table 3: I/O Bank Pairs and Shared Vcco Pins
Pins labeled I0_VREF can be used as either in all parts
unless device-dependent, as indicated in the footnotes. If
the pin is not used as V
Immediately following
Pair information.
Table 4: CS144 — XCV50E, XCV100E, XCV200E
Module 4 of 4
4
Bank
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
CCO
Paired Banks
. See
Banks 0 & 1
Banks 2 & 3
Banks 4 & 5
Banks 6 & 7
Table
IO_WRITE_L5N_YY
IO_LVDS_DLL_L2N
IO_LVDS_DLL_L2P
IO_VREF_L0N_YY
IO_VREF_L4P_YY
3.
Pin Description
IO_CS_L5P_YY
Table
IO_L0P_YY
IO_L1N_YY
IO_L1P_YY
IO_L3N_YY
IO_L3P_YY
IO_L4N_YY
REF
IO_VREF
IO_VREF
IO_VREF
GCK3
GCK2
, it can be used as general I/O.
IO
IO
4, see
Shared V
B12, G11, M13
Table 5
N1, N7, N13
A2, A13, D7
B2, G2, M2
CCO
is Differential
Pins
Pin #
C10
D10
D9
B4
A3
A6
B3
A4
B5
A5
C6
C4
D6
A7
A8
B7
C8
D8
C9
www.xilinx.com
1-800-255-7778
2
1
2
Table 4: CS144 — XCV50E, XCV100E, XCV200E
Bank
1
1
1
2
2
2
2
2
2
2
2
2
2
2
2
2
3
3
3
3
3
3
3
3
3
3
3
3
3
4
4
4
IO_DOUT_BUSY_L6P_YY
IO_DIN_D0_L6N_YY
IO_INIT_L14N_YY
IO_D5_L12N_YY
IO_D7_L14P_YY
Pin Description
IO_D2_L8P_YY
IO_VREF_L11N
IO_VREF_L13N
IO_VREF_L7P
IO_VREF_L9P
IO_D4_L11P
IO_L12P_YY
IO_D6_L13P
IO_D1_L7N
IO_L8N_YY
IO_D3_L9N
IO_VREF
IO_VREF
IO_VREF
IO_VREF
IO_VREF
IO_VREF
IO_VREF
IO_L10P
IO_L10N
GCK0
Production Product Specification
IO
IO
IO
IO
IO
IO
DS022-4 (v2.5) March 14, 2003
Pin #
B10
D13
C13
K11
J10
M10
A10
D12
C11
C12
E12
D11
H13
G13
H11
H12
H10
K12
F12
E10
E13
F11
F10
F13
K13
K10
J13
J11
L13
M8
B8
K7
2
1
2
1
1
R