EZ80F920120MOD Zilog, EZ80F920120MOD Datasheet - Page 248
EZ80F920120MOD
Manufacturer Part Number
EZ80F920120MOD
Description
MODULE EZ80F92 512K 20MHZ
Manufacturer
Zilog
Datasheets
1.EZ80F920120MOD.pdf
(269 pages)
2.EZ80F920120MOD.pdf
(4 pages)
3.EZ80F920120MOD.pdf
(2 pages)
Specifications of EZ80F920120MOD
Module/board Type
Development Module
Processor Series
EZ80F92x
Core
eZ80
Data Bus Width
8 bit
Program Memory Type
Flash
Program Memory Size
1 MB
Interface Type
Cable
Maximum Clock Frequency
20 MHz
Operating Supply Voltage
0 V to 3.3 V
Maximum Operating Temperature
+ 70 C
Mounting Style
SMD/SMT
Package / Case
LQFP
Development Tools By Supplier
eZ80F920200ZCOG
Minimum Operating Temperature
0 C
For Use With/related Products
eZ80F92
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Other names
269-3157
EZ80F920120MOD
EZ80F920120MOD
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PS015308-0404
Table 150. External Write Timing
Parameter
T
T
T
T
T
T
T
T
T
T
Note: *At the conclusion of a Write cycle, deassertion of WR always occurs before any change to
1
2
3
4
5
6
7
8
9
10
ADDR, DATA, CSx, or MREQ.
Abbreviation
Clock Rise to ADDR Valid Delay
Clock Rise to ADDR Hold Time
Clock Fall to Output DATA Valid Delay
Clock Rise to DATA Hold Time
Clock Rise to CSx Assertion Delay
Clock Rise to CSx Deassertion Delay
Clock Rise to MREQ Assertion Delay
Clock Rise to MREQ Deassertion Delay
Clock Fall to WR Assertion Delay
Clock Rise to WR Deassertion Delay*
WR Deassertion to ADDR Hold Time
WR Deassertion to DATA Hold Time
WR Deassertion to CSx Hold Time
WR Deassertion to MREQ Hold Time
P R E L I M I N A R Y
—
2.0
—
2.0
2.0
2.0
2.0
2.0
1.8
1.6
0.25
0.25
0.25
0.25
Product Specification
Min
Electrical Characteristics
eZ80F92/eZ80F93
Delay (ns)
13
—
11
—
19.0
18.0
16.0
16.0
6.5
6.5
—
—
—
—
Max
236
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