EZ80F920120MOD Zilog, EZ80F920120MOD Datasheet - Page 90

• Manufacturer Part Number: EZ80F920120MOD
• Description: MODULE EZ80F92 512K 20MHZ
• Manufacturer: Zilog

Specifications of EZ80F920120MOD

• Module/board Type: Development Module
• Processor Series: EZ80F92x
• Core: eZ80
• Data Bus Width: 8 bit
• Program Memory Type: Flash
• Program Memory Size: 1 MB
• Interface Type: Cable
• Maximum Clock Frequency: 20 MHz
• Operating Supply Voltage: 0 V to 3.3 V
• Maximum Operating Temperature: + 70 C
• Mounting Style: SMD/SMT
• Package / Case: LQFP
• Development Tools By Supplier: eZ80F920200ZCOG
• Minimum Operating Temperature: 0 C
• For Use With/related Products: eZ80F92
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Other names: 269-3157; EZ80F920120MOD

Programmable Reload Timers
Figure 20.Programmable Reload Timer Block Diagram
PS015308-0404
System Clock
RTC Source
GPIO Pin
Programmable Reload Timers Overview
(Timers 0–3
TMRx_IN
The eZ80F92 device features six Programmable Reload Timers (PRT). Each PRT contains
a 16-bit downcounter and a 16-bit reload register. In addition, each PRT features a clock
prescaler with four selectable taps for CLK ÷ 4, CLK ÷ 16, CLK ÷ 64, and CLK ÷ 256.
Each timer can be individually enabled to operate in either SINGLE PASS or CONTINU-
OUS mode. The timer can be programmed to start, stop, restart from the current value, or
restart from the initial value, and generate interrupts to the CPU.
Four of the Programmable Reload Timers (timers 0–3) feature a selectable clock source
input. The input for these timers can be either the system clock or the Real-Time Clock
(RTC) source. Timers 0–3 can also be used for event counting, with their inputs received
from a GPIO port pin. Output from timers 4 and 5 can be directed to a GPIO port pin.
Each of the six PRTs available on the eZ80F92 device can be controlled individually. They
do not share the same counters, reload registers, control registers, or interrupt signals. A
simplified block diagram of a programmable reload timer is illustrated in Figure 20.
only)
2
TMRx_CTL[3:2]
Adjustable
Prescaler
Clock
2
{TMRx_RR_H, TMRx_RR_L}
{TMRx_DR_H, TMRx_DR_L}
P R E L I M I N A R Y
Reload Registers
Data Registers
Down Counter
Data[7:0]
Data[7:0]
16-Bit
Control Register
Control Logic
TMRx_CTL
Data[7:0]
PRT
(Timers 4–5 only)
Programmable Reload Timers
TOUT_EN
Product Specification
eZ80F92/eZ80F93
IRQ to eZ80 CPU
Timer Out
78