MPC8343VRAGDB Freescale Semiconductor, MPC8343VRAGDB Datasheet - Page 2

IC MPU POWERQUICC II 620-PBGA

MPC8343VRAGDB

Manufacturer Part Number
MPC8343VRAGDB
Description
IC MPU POWERQUICC II 620-PBGA
Manufacturer
Freescale Semiconductor
Series
PowerQUICC II PROr
Datasheet

Specifications of MPC8343VRAGDB

Processor Type
MPC83xx PowerQUICC II Pro 32-Bit
Speed
400MHz
Voltage
1.2V
Mounting Type
Surface Mount
Package / Case
620-PBGA
Processor Series
MPC8xxx
Core
e300
Data Bus Width
32 bit
Development Tools By Supplier
MPC8349E-MITXE
Maximum Clock Frequency
400 MHz
Maximum Operating Temperature
+ 105 C
Mounting Style
SMD/SMT
I/o Voltage
1.8 V, 2.5 V, 3.3 V
Minimum Operating Temperature
0 C
Core Size
32 Bit
Program Memory Size
64KB
Cpu Speed
400MHz
Embedded Interface Type
I2C, SPI, USB, UART
Digital Ic Case Style
BGA
No. Of Pins
620
Rohs Compliant
Yes
Family Name
MPC83xx
Device Core
PowerQUICC II Pro
Device Core Size
32b
Frequency (max)
400MHz
Instruction Set Architecture
RISC
Supply Voltage 1 (typ)
1.2V
Operating Supply Voltage (max)
1.26V
Operating Supply Voltage (min)
1.14V
Operating Temp Range
0C to 105C
Operating Temperature Classification
Commercial
Mounting
Surface Mount
Pin Count
620
Package Type
BGA
For Use With
CWH-PPC-8343N-VX - KIT EVAL SYSTEM QUICCSTART 8248CWH-PPC-8343N-VE - EVALUATION SYSTEM QUICC MPC8343E
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Features
-
Lead Free Status / Rohs Status
Lead free / RoHS Compliant

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Overview
1
This section provides a high-level overview of the device features.
units within the MPC8343EA.
Major features of the device are as follows:
2
Overview
Embedded PowerPC e300 processor core; operates at up to 400 MHz
— High-performance, superscalar processor core
— Floating-point, integer, load/store, system register, and branch processing units
— 32-Kbyte instruction cache, 32-Kbyte data cache
— Lockable portion of L1 cache
— Dynamic power management
— Software-compatible with the other Freescale processor families that implement Power
Double data rate, DDR1/DDR2 SDRAM memory controller
— Programmable timing supporting DDR1 and DDR2 SDRAM
— 32- bit data interface, up to 266 MHz data rate
Architecture technology
MPC8343EA PowerQUICC II Pro Integrated Host Processor Hardware Specifications, Rev. 10
The information in this document is accurate for revision 3.x silicon and
later (in other words, for orderable part numbers ending in A or B). For
information on revision 1.1 silicon and earlier versions, see the MPC8343E
PowerQUICC II Pro Integrated Host Processor Hardware Specifications.
See
silicon revision level determination.
Security
Dual
Role
High-Speed
USB 2.0
Section 22.1, “Part Numbers Fully Addressed by This Document,”
Dual I
DUART
Timers
GPIO
2
C
10/100/1000
Figure 1. MPC8343EA Block Diagram
Ethernet
Controller
Interrupt
10/100/1000
D-Cache
NOTE
Ethernet
32KB
e300 Core
I-Cache
32KB
PCI
Figure 1
Local Bus
SEQ
shows the major functional
Controller
SDRAM
Freescale Semiconductor
DDR
DMA
for

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