MPC8343VRAGDB Freescale Semiconductor, MPC8343VRAGDB Datasheet - Page 48

• Manufacturer Part Number: MPC8343VRAGDB
• Description: IC MPU POWERQUICC II 620-PBGA
• Manufacturer: Freescale Semiconductor
• Series: PowerQUICC II PROr

Specifications of MPC8343VRAGDB

• Processor Type: MPC83xx PowerQUICC II Pro 32-Bit
• Speed: 400MHz
• Voltage: 1.2V
• Mounting Type: Surface Mount
• Package / Case: 620-PBGA
• Processor Series: MPC8xxx
• Core: e300
• Data Bus Width: 32 bit
• Development Tools By Supplier: MPC8349E-MITXE
• Maximum Clock Frequency: 400 MHz
• Maximum Operating Temperature: + 105 C
• Mounting Style: SMD/SMT
• I/o Voltage: 1.8 V, 2.5 V, 3.3 V
• Minimum Operating Temperature: 0 C
• Core Size: 32 Bit
• Program Memory Size: 64KB
• Cpu Speed: 400MHz
• Embedded Interface Type: I2C, SPI, USB, UART
• Digital Ic Case Style: BGA
• No. Of Pins: 620
• Rohs Compliant: Yes
• Family Name: MPC83xx
• Device Core: PowerQUICC II Pro
• Device Core Size: 32b
• Frequency (max): 400MHz
• Instruction Set Architecture: RISC
• Supply Voltage 1 (typ): 1.2V
• Operating Supply Voltage (max): 1.26V
• Operating Supply Voltage (min): 1.14V
• Operating Temp Range: 0C to 105C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 620
• Package Type: BGA
• For Use With: CWH-PPC-8343N-VX - KIT EVAL SYSTEM QUICCSTART 8248CWH-PPC-8343N-VE - EVALUATION SYSTEM QUICC MPC8343E
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Features: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

Package and Pin Listings
Figure 33
generally reference the rising edge of the clock, these AC timing diagrams also apply when the falling edge
is the active edge.
Figure 33
Figure 34
18 Package and Pin Listings
This section details package parameters, pin assignments, and dimensions. The MPC8343EA is available
in a plastic ball grid array (PBGA). See
and
18.1
The package parameters are as provided in the following list. The package type is 29 mm × 29 mm,
620 plastic ball grid array (PBGA).
48
Section 18.2, “Mechanical Dimensions for the MPC8343EA PBGA.”
Package outline
Interconnects
Pitch
Module height (maximum)
Note: The clock edge is selectable on SPI.
Note: The clock edge is selectable on SPI.
SPICLK (Output)
and
shows the SPI timings in slave mode (external clock).
Output Signals:
shows the SPI timings in master mode (internal clock).
SPICLK (Input)
Output Signals:
MPC8343EA PowerQUICC II Pro Integrated Host Processor Hardware Specifications, Rev. 10
Input Signals:
Input Signals:
Package Parameters for the MPC8343EA PBGA
(See Note)
(See Note)
Figure 34
(See Note)
(See Note)
SPIMOSI
SPIMISO
SPIMISO
SPIMOSI
Figure 34. SPI AC Timing in Master Mode (Internal Clock) Diagram
Figure 33. SPI AC Timing in Slave Mode (External Clock) Diagram
represent the AC timings from
t
NEIVKH
t
NIIVKH
Section 18.1, “Package Parameters for the MPC8343EA PBGA,”
t
NIKHOX
620
1.00 mm
2.46 mm
29 mm × 29 mm
t
NIIXKH
t
NEKHOX
t
NEIXKH
Table
50. Note that although the specifications
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