MPC8343VRAGDB Freescale Semiconductor, MPC8343VRAGDB Datasheet - Page 24

• Manufacturer Part Number: MPC8343VRAGDB
• Description: IC MPU POWERQUICC II 620-PBGA
• Manufacturer: Freescale Semiconductor
• Series: PowerQUICC II PROr

Specifications of MPC8343VRAGDB

• Processor Type: MPC83xx PowerQUICC II Pro 32-Bit
• Speed: 400MHz
• Voltage: 1.2V
• Mounting Type: Surface Mount
• Package / Case: 620-PBGA
• Processor Series: MPC8xxx
• Core: e300
• Data Bus Width: 32 bit
• Development Tools By Supplier: MPC8349E-MITXE
• Maximum Clock Frequency: 400 MHz
• Maximum Operating Temperature: + 105 C
• Mounting Style: SMD/SMT
• I/o Voltage: 1.8 V, 2.5 V, 3.3 V
• Minimum Operating Temperature: 0 C
• Core Size: 32 Bit
• Program Memory Size: 64KB
• Cpu Speed: 400MHz
• Embedded Interface Type: I2C, SPI, USB, UART
• Digital Ic Case Style: BGA
• No. Of Pins: 620
• Rohs Compliant: Yes
• Family Name: MPC83xx
• Device Core: PowerQUICC II Pro
• Device Core Size: 32b
• Frequency (max): 400MHz
• Instruction Set Architecture: RISC
• Supply Voltage 1 (typ): 1.2V
• Operating Supply Voltage (max): 1.26V
• Operating Supply Voltage (min): 1.14V
• Operating Temp Range: 0C to 105C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 620
• Package Type: BGA
• For Use With: CWH-PPC-8343N-VX - KIT EVAL SYSTEM QUICCSTART 8248CWH-PPC-8343N-VE - EVALUATION SYSTEM QUICC MPC8343E
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Features: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

Ethernet: Three-Speed Ethernet, MII Management
8.2.1.2
Table 26
Figure 9
Figure 10
24
At recommended operating conditions with LV
RX_CLK clock period 10 Mbps
RX_CLK clock period 100 Mbps
RX_CLK duty cycle
RXD[3:0], RX_DV, RX_ER setup time to RX_CLK
RXD[3:0], RX_DV, RX_ER hold time to RX_CLK
RX_CLK clock rise (20%–80%)
RX_CLK clock fall time (80%–20%)
Note:
1. The symbols for timing specifications follow the pattern of t
and t
(MR) with respect to the time data input signals (D) reach the valid state (V) relative to the t
the high (H) state or setup time. Also, t
(D) went invalid (X) relative to the t
reference symbol is based on three letters representing the clock of a particular function. For example, the subscript of t
represents the MII (M) receive (RX) clock. For rise and fall times, the latter convention is used with the appropriate letter:
R (rise) or F (fall).
(first two letters of functional block)(reference)(state)(signal)(state)
provides the AC test load for TSEC.
provides the MII receive AC timing specifications.
shows the MII receive AC timing diagram.
MPC8343EA PowerQUICC II Pro Integrated Host Processor Hardware Specifications, Rev. 10
MII Receive AC Timing Specifications
RXD[3:0]
Parameter/Condition
RX_CLK
RX_DV
RX_ER
Output
Table 26. MII Receive AC Timing Specifications
MRX
Figure 10. MII Receive AC Timing Diagram
t
t
MRXH
MRDVKH
DD
MRDXKL
clock reference (K) going to the low (L) state or hold time. In general, the clock
/OV
Figure 9. TSEC AC Test Load
t
DD
MRX
symbolizes MII receive timing (GR) with respect to the time data input signals
of 3.3 V ± 10%.
Z
0
= 50 Ω
Valid Data
for outputs. For example, t
(first two letters of functional block)(signal)(state)(reference)(state)
t
MRXH
Symbol
t
t
t
MRXF
MRDVKH
MRDXKH
t
t
t
t
MRXR
MRXF
MRX
MRX
/t
MRX
1
R
t
MRDXKH
L
t
MRXR
= 50 Ω
10.0
10.0
Min
1.0
1.0
35
—
—
MRDVKH
OV
MRX
DD
Typ
400
40
—
—
—
—
—
symbolizes MII receive timing
/2
clock reference (K) going to
Freescale Semiconductor
Max
4.0
4.0
—
—
65
—
—
for inputs
Unit
ns
ns
ns
ns
ns
ns
%
MRX