MPC8343VRAGDB Freescale Semiconductor, MPC8343VRAGDB Datasheet - Page 36

IC MPU POWERQUICC II 620-PBGA

MPC8343VRAGDB

Manufacturer Part Number
MPC8343VRAGDB
Description
IC MPU POWERQUICC II 620-PBGA
Manufacturer
Freescale Semiconductor
Series
PowerQUICC II PROr
Datasheet

Specifications of MPC8343VRAGDB

Processor Type
MPC83xx PowerQUICC II Pro 32-Bit
Speed
400MHz
Voltage
1.2V
Mounting Type
Surface Mount
Package / Case
620-PBGA
Processor Series
MPC8xxx
Core
e300
Data Bus Width
32 bit
Development Tools By Supplier
MPC8349E-MITXE
Maximum Clock Frequency
400 MHz
Maximum Operating Temperature
+ 105 C
Mounting Style
SMD/SMT
I/o Voltage
1.8 V, 2.5 V, 3.3 V
Minimum Operating Temperature
0 C
Core Size
32 Bit
Program Memory Size
64KB
Cpu Speed
400MHz
Embedded Interface Type
I2C, SPI, USB, UART
Digital Ic Case Style
BGA
No. Of Pins
620
Rohs Compliant
Yes
Family Name
MPC83xx
Device Core
PowerQUICC II Pro
Device Core Size
32b
Frequency (max)
400MHz
Instruction Set Architecture
RISC
Supply Voltage 1 (typ)
1.2V
Operating Supply Voltage (max)
1.26V
Operating Supply Voltage (min)
1.14V
Operating Temp Range
0C to 105C
Operating Temperature Classification
Commercial
Mounting
Surface Mount
Pin Count
620
Package Type
BGA
For Use With
CWH-PPC-8343N-VX - KIT EVAL SYSTEM QUICCSTART 8248CWH-PPC-8343N-VE - EVALUATION SYSTEM QUICC MPC8343E
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Features
-
Lead Free Status / Rohs Status
Lead free / RoHS Compliant

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JTAG
11 JTAG
This section describes the DC and AC electrical specifications for the IEEE Std. 1149.1 (JTAG) interface
of the MPC8343EA.
11.1
Table 36
MPC8343EA.
36
Input high voltage
Input low voltage
Input current
Output high voltage
GPCM Mode Output Signals:
LCS[0:3]/LBS[0:3]/LGPL[0:5]
UPM Mode Output Signals:
provides the DC electrical characteristics for the IEEE Std. 1149.1 (JTAG) interface of the
Figure 21. Local Bus Signals, GPCM/UPM Signals for LCCR[CLKDIV] = 4 (DLL Enabled)
JTAG DC Electrical Characteristics
UPM Mode Input Signal:
MPC8343EA PowerQUICC II Pro Integrated Host Processor Hardware Specifications, Rev. 10
LAD[0:31]/LDP[0:3]
Parameter
LCS[0:3]/LWE
Input Signals:
LSYNC_IN
LUPWAIT
Table 36. JTAG Interface DC Electrical Characteristics
T1
T2
T3
T4
t
t
LBKHOV1
LBKHOV1
Symbol
V
V
V
I
t
t
OH
LBIVKH2
LBIVKH1
IN
IH
IL
t
t
LBKHOZ1
LBKHOZ1
I
OH
Condition
= –8.0 mA
t
t
LBIXKH2
LBIXKH1
OV
DD
–0.3
Min
2.4
– 0.3
Freescale Semiconductor
OV
DD
Max
0.8
±5
+ 0.3
Unit
μA
V
V
V

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