MPC8343VRAGDB Freescale Semiconductor, MPC8343VRAGDB Datasheet - Page 33

• Manufacturer Part Number: MPC8343VRAGDB
• Description: IC MPU POWERQUICC II 620-PBGA
• Manufacturer: Freescale Semiconductor
• Series: PowerQUICC II PROr

Specifications of MPC8343VRAGDB

• Processor Type: MPC83xx PowerQUICC II Pro 32-Bit
• Speed: 400MHz
• Voltage: 1.2V
• Mounting Type: Surface Mount
• Package / Case: 620-PBGA
• Processor Series: MPC8xxx
• Core: e300
• Data Bus Width: 32 bit
• Development Tools By Supplier: MPC8349E-MITXE
• Maximum Clock Frequency: 400 MHz
• Maximum Operating Temperature: + 105 C
• Mounting Style: SMD/SMT
• I/o Voltage: 1.8 V, 2.5 V, 3.3 V
• Minimum Operating Temperature: 0 C
• Core Size: 32 Bit
• Program Memory Size: 64KB
• Cpu Speed: 400MHz
• Embedded Interface Type: I2C, SPI, USB, UART
• Digital Ic Case Style: BGA
• No. Of Pins: 620
• Rohs Compliant: Yes
• Family Name: MPC83xx
• Device Core: PowerQUICC II Pro
• Device Core Size: 32b
• Frequency (max): 400MHz
• Instruction Set Architecture: RISC
• Supply Voltage 1 (typ): 1.2V
• Operating Supply Voltage (max): 1.26V
• Operating Supply Voltage (min): 1.14V
• Operating Temp Range: 0C to 105C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 620
• Package Type: BGA
• For Use With: CWH-PPC-8343N-VX - KIT EVAL SYSTEM QUICCSTART 8248CWH-PPC-8343N-VE - EVALUATION SYSTEM QUICC MPC8343E
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Features: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

Figure 16
Freescale Semiconductor
LA[27:31]/LBCTL/LBCKE/LOE
LA[27:31]/LBCTL/LBCKE/LOE
LSDA10/LSDWE/LSDRAS/
through
MPC8343EA PowerQUICC II Pro Integrated Host Processor Hardware Specifications, Rev. 10
LSDA10/LSDWE/LSDRAS/
Output (Address) Signal:
LSDCAS/LSDDQM[0:3]
Output (Data) Signals:
LSDCAS/LSDDQM[0:3]
Figure 17. Local Bus Signals, Nonspecial Signals Only (DLL Bypass Mode)
LAD[0:31]/LDP[0:3]
LAD[0:31]/LDP[0:3]
LAD[0:31]/LDP[0:3]
LAD[0:31]/LDP[0:3]
Figure 16. Local Bus Signals, Nonspecial Signals Only (DLL Enabled)
Figure 21
Output Signals:
Input Signals:
Output Signals:
Output Signals:
Input Signals:
LSYNC_IN
LAD[0:31]
Input Signal:
LCLK[n]
LALE
show the local bus signals.
LGTA
LALE
t
t
LBKHOV
LBKHOV
t
t
t
LBKLOV
LBKHOV
LBKHLR
t
LBKLOV
t
LBKLOV
t
t
t
LBIVKH
LBKHOX
LBKHOX
t
t
LBKHOZ
LBKHOZ
t
LBOTOT
t
LBKHOZ
t
LBIXKH
t
LBOTOT
t
LBIVKH
t
t
LBIXKH
LBIXKH
t
LBIVKH
t
LBIXKH
Local Bus
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